Array-Level Programming of 3-Bit per Cell Resistive Memory and Its Application for Deep Neural Network Inference

Yandong Luo, Xu Han, Zhilu Ye, Hugh Barnaby, Jae Sun Seo, Shimeng Yu

Research output: Contribution to journalArticlepeer-review

2 Scopus citations

Abstract

The requirement of multilevel cell (MLC) resistive random access memory (RRAM) for computing is different than that for MLC storage. It generally requires a linearly spaced conductance median and an ultratight conductance distribution, as the column current are summed up for analog computation. In this article, 3-bit per cell RRAM that is suitable for accurate inference of a deep neural network (DNN) is demonstrated, with ultratight conductance distribution (<1.5% sigma). First, a two-loop write-verify protocol is proposed. Then, statistical experiments are conducted on RRAM array fabricated in Winbond's 90-nm process. By incorporating the measured conductance distribution into DNN simulation considering the real weight mapping, inference accuracy with only 0.5% degradation over software baseline is achieved for CIFAR-10 data set even when 128 rows are read-out in parallel. By enabling parallel read-out, the system-level energy efficiency and throughput could be improved by 5.3 \times and 4.4 \times , respectively, compared to the 3-bit per cell RRAM used as MLC storage.

Original languageEnglish (US)
Article number9174666
Pages (from-to)4621-4625
Number of pages5
JournalIEEE Transactions on Electron Devices
Volume67
Issue number11
DOIs
StatePublished - Nov 2020

Keywords

  • Compute-in-memory (CIM)
  • deep neural network (DNN)
  • multilevel cell (MLC)
  • resistive random access memory (RRAM)

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Fingerprint

Dive into the research topics of 'Array-Level Programming of 3-Bit per Cell Resistive Memory and Its Application for Deep Neural Network Inference'. Together they form a unique fingerprint.

Cite this