Area and Power Efficient Radiation Hard by Design Flip-flop Using Temproal Master and DICE Slave Latches

Lawrence Clark (Inventor)

Research output: Patent

Abstract

Electronic circuits, electronic state storing circuits in particular, are vulnerable to high-energy sub-atomic particles and electromagnetic radiation. Consequently, techniques of radiation hardening the circuits that utilize special circuit designs, circuit layouts, select materials, or any combination thereof, are commonly employed to reduce this vulnerability. While special circuit layering techniques help to mitigate radiation affecting long-term functionality of circuits, the common solution to mitigate short-term effects, such as single event transients (SETs) and single event upset (SEU), involves applying combinations of dual interlocked storage cell (DICE) latches and temporal latches to correct logic states corrupted by the short-term radiation; neither component, alone, provides both adequate and efficient protection to the circuits. DICE latches protect only against SEU, and temporal latches require costs of added circuit area. Researchers at Arizona State University have developed a D-type master-slave flip-flop (MSFF), incorporating both a modified DICE latch and modified temporal latch in a single sequential circuit element, to provide improved radiation hardening against both SETs and SEU. By including fewer delay circuits, the flip-flop occupies less area than a flip-flop using only temporal latches. Meanwhile, the temporal latch protects the inputs of the DICE from upsets due to SET at the sampling clock edge by incorporating an additional majority gate that provides independence to all four storage nodes of the DICE. Overall, this MSFF uses 26 fewer transistors than a flip-flop implemented using only temporal latches, saving significant area and reducing power dissipation by as much as 13%. Heavy ion testing demonstrates over two orders of magnitude reduction in saturation cross section over an unhardened flip-flop and a threshold linear energy transfer (LET) of approximately 30 MeV/gm/cm2. Potential Applications High-Altitude Flight Outer Space Missions & Satellites Military NuclearBenefits and Advantages Offers Substantial Reduction of Radiation Saturation - demonstrates over two magnitude reduction in saturation cross section over an unhardened flip-flop; radiation hardness well in excess of minimum rad-hard specifications Provides Significant Reduction in Occupied Circuit Area (30 - 50% less area) using 26 fewer transistors reduces costs by decreasing the total area occupied; reduces the size of radiation hardened electronic devices Demonstrates Reduction in Power Dissipation (13% reduction) Renders Substantial Linear Energy Transfer (exceeding 30 MeV/gm/cm2) Operates with Standard CMOS ProcessingDownload original PDF
Original languageEnglish (US)
StatePublished - Oct 12 2006

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Flip flop circuits
Radiation
Networks (circuits)
Radiation hardening
Energy transfer
Energy dissipation
Transistors
Military satellites
Delay circuits
Integrated circuit layout
Sequential circuits
Electronic states
Space flight
Heavy ions
Electromagnetic waves
Costs
Clocks
Hardness

Cite this

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title = "Area and Power Efficient Radiation Hard by Design Flip-flop Using Temproal Master and DICE Slave Latches",
abstract = "Electronic circuits, electronic state storing circuits in particular, are vulnerable to high-energy sub-atomic particles and electromagnetic radiation. Consequently, techniques of radiation hardening the circuits that utilize special circuit designs, circuit layouts, select materials, or any combination thereof, are commonly employed to reduce this vulnerability. While special circuit layering techniques help to mitigate radiation affecting long-term functionality of circuits, the common solution to mitigate short-term effects, such as single event transients (SETs) and single event upset (SEU), involves applying combinations of dual interlocked storage cell (DICE) latches and temporal latches to correct logic states corrupted by the short-term radiation; neither component, alone, provides both adequate and efficient protection to the circuits. DICE latches protect only against SEU, and temporal latches require costs of added circuit area. Researchers at Arizona State University have developed a D-type master-slave flip-flop (MSFF), incorporating both a modified DICE latch and modified temporal latch in a single sequential circuit element, to provide improved radiation hardening against both SETs and SEU. By including fewer delay circuits, the flip-flop occupies less area than a flip-flop using only temporal latches. Meanwhile, the temporal latch protects the inputs of the DICE from upsets due to SET at the sampling clock edge by incorporating an additional majority gate that provides independence to all four storage nodes of the DICE. Overall, this MSFF uses 26 fewer transistors than a flip-flop implemented using only temporal latches, saving significant area and reducing power dissipation by as much as 13{\%}. Heavy ion testing demonstrates over two orders of magnitude reduction in saturation cross section over an unhardened flip-flop and a threshold linear energy transfer (LET) of approximately 30 MeV/gm/cm2. Potential Applications High-Altitude Flight Outer Space Missions & Satellites Military NuclearBenefits and Advantages Offers Substantial Reduction of Radiation Saturation - demonstrates over two magnitude reduction in saturation cross section over an unhardened flip-flop; radiation hardness well in excess of minimum rad-hard specifications Provides Significant Reduction in Occupied Circuit Area (30 - 50{\%} less area) using 26 fewer transistors reduces costs by decreasing the total area occupied; reduces the size of radiation hardened electronic devices Demonstrates Reduction in Power Dissipation (13{\%} reduction) Renders Substantial Linear Energy Transfer (exceeding 30 MeV/gm/cm2) Operates with Standard CMOS ProcessingDownload original PDF",
author = "Lawrence Clark",
year = "2006",
month = "10",
day = "12",
language = "English (US)",
type = "Patent",

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TY - PAT

T1 - Area and Power Efficient Radiation Hard by Design Flip-flop Using Temproal Master and DICE Slave Latches

AU - Clark, Lawrence

PY - 2006/10/12

Y1 - 2006/10/12

N2 - Electronic circuits, electronic state storing circuits in particular, are vulnerable to high-energy sub-atomic particles and electromagnetic radiation. Consequently, techniques of radiation hardening the circuits that utilize special circuit designs, circuit layouts, select materials, or any combination thereof, are commonly employed to reduce this vulnerability. While special circuit layering techniques help to mitigate radiation affecting long-term functionality of circuits, the common solution to mitigate short-term effects, such as single event transients (SETs) and single event upset (SEU), involves applying combinations of dual interlocked storage cell (DICE) latches and temporal latches to correct logic states corrupted by the short-term radiation; neither component, alone, provides both adequate and efficient protection to the circuits. DICE latches protect only against SEU, and temporal latches require costs of added circuit area. Researchers at Arizona State University have developed a D-type master-slave flip-flop (MSFF), incorporating both a modified DICE latch and modified temporal latch in a single sequential circuit element, to provide improved radiation hardening against both SETs and SEU. By including fewer delay circuits, the flip-flop occupies less area than a flip-flop using only temporal latches. Meanwhile, the temporal latch protects the inputs of the DICE from upsets due to SET at the sampling clock edge by incorporating an additional majority gate that provides independence to all four storage nodes of the DICE. Overall, this MSFF uses 26 fewer transistors than a flip-flop implemented using only temporal latches, saving significant area and reducing power dissipation by as much as 13%. Heavy ion testing demonstrates over two orders of magnitude reduction in saturation cross section over an unhardened flip-flop and a threshold linear energy transfer (LET) of approximately 30 MeV/gm/cm2. Potential Applications High-Altitude Flight Outer Space Missions & Satellites Military NuclearBenefits and Advantages Offers Substantial Reduction of Radiation Saturation - demonstrates over two magnitude reduction in saturation cross section over an unhardened flip-flop; radiation hardness well in excess of minimum rad-hard specifications Provides Significant Reduction in Occupied Circuit Area (30 - 50% less area) using 26 fewer transistors reduces costs by decreasing the total area occupied; reduces the size of radiation hardened electronic devices Demonstrates Reduction in Power Dissipation (13% reduction) Renders Substantial Linear Energy Transfer (exceeding 30 MeV/gm/cm2) Operates with Standard CMOS ProcessingDownload original PDF

AB - Electronic circuits, electronic state storing circuits in particular, are vulnerable to high-energy sub-atomic particles and electromagnetic radiation. Consequently, techniques of radiation hardening the circuits that utilize special circuit designs, circuit layouts, select materials, or any combination thereof, are commonly employed to reduce this vulnerability. While special circuit layering techniques help to mitigate radiation affecting long-term functionality of circuits, the common solution to mitigate short-term effects, such as single event transients (SETs) and single event upset (SEU), involves applying combinations of dual interlocked storage cell (DICE) latches and temporal latches to correct logic states corrupted by the short-term radiation; neither component, alone, provides both adequate and efficient protection to the circuits. DICE latches protect only against SEU, and temporal latches require costs of added circuit area. Researchers at Arizona State University have developed a D-type master-slave flip-flop (MSFF), incorporating both a modified DICE latch and modified temporal latch in a single sequential circuit element, to provide improved radiation hardening against both SETs and SEU. By including fewer delay circuits, the flip-flop occupies less area than a flip-flop using only temporal latches. Meanwhile, the temporal latch protects the inputs of the DICE from upsets due to SET at the sampling clock edge by incorporating an additional majority gate that provides independence to all four storage nodes of the DICE. Overall, this MSFF uses 26 fewer transistors than a flip-flop implemented using only temporal latches, saving significant area and reducing power dissipation by as much as 13%. Heavy ion testing demonstrates over two orders of magnitude reduction in saturation cross section over an unhardened flip-flop and a threshold linear energy transfer (LET) of approximately 30 MeV/gm/cm2. Potential Applications High-Altitude Flight Outer Space Missions & Satellites Military NuclearBenefits and Advantages Offers Substantial Reduction of Radiation Saturation - demonstrates over two magnitude reduction in saturation cross section over an unhardened flip-flop; radiation hardness well in excess of minimum rad-hard specifications Provides Significant Reduction in Occupied Circuit Area (30 - 50% less area) using 26 fewer transistors reduces costs by decreasing the total area occupied; reduces the size of radiation hardened electronic devices Demonstrates Reduction in Power Dissipation (13% reduction) Renders Substantial Linear Energy Transfer (exceeding 30 MeV/gm/cm2) Operates with Standard CMOS ProcessingDownload original PDF

M3 - Patent

ER -