Abstract

A wide range of architectures for computing 1-D and 2-D DWT, and 1-D and 2-D CWT are presented. These architectures range from systolic arrays and parallel filters to SIMD arrays. The systolic array and the parallel filter architectures require an area that is independent of the length of the input sequence, and support single chip implementation. The SIMD architectures, on the other hand, are optimized for time, and have an area that is proportional to the size of the input.

Original languageEnglish (US)
Title of host publicationProceedings of IEEE Workshop on VLSI Signal Processing VI, VLSISP 1993
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages507-515
Number of pages9
ISBN (Electronic)0780309960, 9780780309968
DOIs
StatePublished - Jan 1 1993
Event6th IEEE Workshop on VLSI Signal Processing, VLSISP 1993 - Veldhoven, Netherlands
Duration: Oct 20 1993Oct 22 1993

Publication series

NameProceedings of IEEE Workshop on VLSI Signal Processing VI, VLSISP 1993

Conference

Conference6th IEEE Workshop on VLSI Signal Processing, VLSISP 1993
CountryNetherlands
CityVeldhoven
Period10/20/9310/22/93

ASJC Scopus subject areas

  • Hardware and Architecture
  • Signal Processing
  • Software

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  • Cite this

    Chakrabarti, C., Vishwanath, M., & Owens, R. (1993). Architectures for wavelet transforms. In Proceedings of IEEE Workshop on VLSI Signal Processing VI, VLSISP 1993 (pp. 507-515). [404454] (Proceedings of IEEE Workshop on VLSI Signal Processing VI, VLSISP 1993). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSISP.1993.404454