Abstract
A wide range of architectures for computing 1-D and 2-D DWT, and 1-D and 2-D CWT are presented. These architectures range from systolic arrays and parallel filters to SIMD arrays. The systolic array and the parallel filter architectures require an area that is independent of the length of the input sequence, and support single chip implementation. The SIMD architectures, on the other hand, are optimized for time, and have an area that is proportional to the size of the input.
| Original language | English (US) |
|---|---|
| Title of host publication | Proceedings of IEEE Workshop on VLSI Signal Processing VI, VLSISP 1993 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 507-515 |
| Number of pages | 9 |
| ISBN (Electronic) | 0780309960, 9780780309968 |
| DOIs | |
| State | Published - Jan 1 1993 |
| Event | 6th IEEE Workshop on VLSI Signal Processing, VLSISP 1993 - Veldhoven, Netherlands Duration: Oct 20 1993 → Oct 22 1993 |
Publication series
| Name | Proceedings of IEEE Workshop on VLSI Signal Processing VI, VLSISP 1993 |
|---|
Conference
| Conference | 6th IEEE Workshop on VLSI Signal Processing, VLSISP 1993 |
|---|---|
| Country | Netherlands |
| City | Veldhoven |
| Period | 10/20/93 → 10/22/93 |
ASJC Scopus subject areas
- Hardware and Architecture
- Signal Processing
- Software
Fingerprint Dive into the research topics of 'Architectures for wavelet transforms'. Together they form a unique fingerprint.
Cite this
Chakrabarti, C., Vishwanath, M., & Owens, R. (1993). Architectures for wavelet transforms. In Proceedings of IEEE Workshop on VLSI Signal Processing VI, VLSISP 1993 (pp. 507-515). [404454] (Proceedings of IEEE Workshop on VLSI Signal Processing VI, VLSISP 1993). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSISP.1993.404454