TY - GEN
T1 - Architecture-aware LDPC code design for software defined radio
AU - Zhu, Yuming
AU - Chakrabarti, Chaitali
PY - 2006/12/1
Y1 - 2006/12/1
N2 - Low-Density Parity-Check (LDPC) codes have been adopted in the physical layer of many communication systems because of their superior performance. The direct implementation of these codes onto an existing software defined radio (SDR) platform is likely to be inefficient. Our approach is to design the LDPC code to match the constraints imposed by the existing architecture, with-out compromising the communication performance. We present a procedure for architecture-aware code design that involves feature identification, code construction and verification. Details of the procedure for the case when the SDR platform is equipped with a multi-stage interconnection network (MIN) is presented. By analyzing the characteristics of the MIN, simple yet explicit constraints are derived and used in the code construction step. The resulting LDPC code can not only be mapped very efficiently onto the SDR platform but also has very good bit error rate (BER) performance.
AB - Low-Density Parity-Check (LDPC) codes have been adopted in the physical layer of many communication systems because of their superior performance. The direct implementation of these codes onto an existing software defined radio (SDR) platform is likely to be inefficient. Our approach is to design the LDPC code to match the constraints imposed by the existing architecture, with-out compromising the communication performance. We present a procedure for architecture-aware code design that involves feature identification, code construction and verification. Details of the procedure for the case when the SDR platform is equipped with a multi-stage interconnection network (MIN) is presented. By analyzing the characteristics of the MIN, simple yet explicit constraints are derived and used in the code construction step. The resulting LDPC code can not only be mapped very efficiently onto the SDR platform but also has very good bit error rate (BER) performance.
UR - http://www.scopus.com/inward/record.url?scp=46249098033&partnerID=8YFLogxK
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U2 - 10.1109/SIPS.2006.352617
DO - 10.1109/SIPS.2006.352617
M3 - Conference contribution
AN - SCOPUS:46249098033
SN - 1424403820
SN - 9781424403820
T3 - 2006 IEEE Workshop on Signal Processing Systems Design and Implementation, SIPS
SP - 405
EP - 410
BT - 2006 IEEE Workshop on Signal Processing Systems Design and Implementation, SIPS
T2 - IEEE Workshop on Signal Processing Systems, SIPS 2006
Y2 - 2 October 2006 through 4 October 2006
ER -