Architecture-aware LDPC code design for software defined radio

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Scopus citations

Abstract

Low-Density Parity-Check (LDPC) codes have been adopted in the physical layer of many communication systems because of their superior performance. The direct implementation of these codes onto an existing software defined radio (SDR) platform is likely to be inefficient. Our approach is to design the LDPC code to match the constraints imposed by the existing architecture, with-out compromising the communication performance. We present a procedure for architecture-aware code design that involves feature identification, code construction and verification. Details of the procedure for the case when the SDR platform is equipped with a multi-stage interconnection network (MIN) is presented. By analyzing the characteristics of the MIN, simple yet explicit constraints are derived and used in the code construction step. The resulting LDPC code can not only be mapped very efficiently onto the SDR platform but also has very good bit error rate (BER) performance.

Original languageEnglish (US)
Title of host publication2006 IEEE Workshop on Signal Processing Systems Design and Implementation, SIPS
Pages405-410
Number of pages6
DOIs
StatePublished - Dec 1 2006
EventIEEE Workshop on Signal Processing Systems, SIPS 2006 - Banff, AB, Canada
Duration: Oct 2 2006Oct 4 2006

Publication series

Name2006 IEEE Workshop on Signal Processing Systems Design and Implementation, SIPS

Other

OtherIEEE Workshop on Signal Processing Systems, SIPS 2006
CountryCanada
CityBanff, AB
Period10/2/0610/4/06

ASJC Scopus subject areas

  • Signal Processing
  • Control and Systems Engineering
  • Electrical and Electronic Engineering

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