Architectural and micro-architectural techniques for software controlled microprocessor soft-error mitigation

Anudeep R. Gogulamudi; Lawrence T. Clark; Chad Farnsworth; Srivatsan Chellappa; Vinay Vashishtha

doi:10.1109/RADECS.2015.7365588

Architectural and micro-architectural techniques for software controlled microprocessor soft-error mitigation

Anudeep R. Gogulamudi, Lawrence T. Clark, Chad Farnsworth, Srivatsan Chellappa, Vinay Vashishtha

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Scopus citations

Abstract

A MIPS 4Kc compliant embedded microprocessor core design that incorporates architectural features for software controlled radiation upset recovery is presented. The design uses fault tolerance techniques, i.e., error detection and instruction restart, implemented at the micro-Architectural level, with architectural level changes, i.e., new instructions, for error recovery. Fine-grained, self-correcting triple mode redundant circuits protect key architectural state, in addition to dual mode redundancy in the instruction execution pipelines, cache subsystems, and error detection and correction in the register file. The design is implemented in a commercial low standby power 90-nm bulk low standby power CMOS process and the prototype operates at up to 336 MHz.

Original language	English (US)
Title of host publication	2015 15th European Conference on Radiation and Its Effects on Components and Systems, RADECS 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
Volume	2015-December
ISBN (Electronic)	9781509002313
DOIs	https://doi.org/10.1109/RADECS.2015.7365588
State	Published - Dec 24 2015
Externally published	Yes
Event	15th European Conference on Radiation and Its Effects on Components and Systems, RADECS 2015 - Moscow, Russian Federation Duration: Sep 14 2015 → Sep 18 2015

Other

Other	15th European Conference on Radiation and Its Effects on Components and Systems, RADECS 2015
Country/Territory	Russian Federation
City	Moscow
Period	9/14/15 → 9/18/15

Keywords

Microprocessor architecture
Radiation hardening
Single event effects
Soft-errors

ASJC Scopus subject areas

Electrical and Electronic Engineering
Radiation

Access to Document

10.1109/RADECS.2015.7365588

Cite this

Gogulamudi, A. R., Clark, L. T., Farnsworth, C., Chellappa, S., & Vashishtha, V. (2015). Architectural and micro-architectural techniques for software controlled microprocessor soft-error mitigation. In 2015 15th European Conference on Radiation and Its Effects on Components and Systems, RADECS 2015 (Vol. 2015-December). Article 7365588 Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/RADECS.2015.7365588

Architectural and micro-architectural techniques for software controlled microprocessor soft-error mitigation. / Gogulamudi, Anudeep R.; Clark, Lawrence T.; Farnsworth, Chad et al.
2015 15th European Conference on Radiation and Its Effects on Components and Systems, RADECS 2015. Vol. 2015-December Institute of Electrical and Electronics Engineers Inc., 2015. 7365588.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Gogulamudi, AR, Clark, LT, Farnsworth, C, Chellappa, S & Vashishtha, V 2015, Architectural and micro-architectural techniques for software controlled microprocessor soft-error mitigation. in 2015 15th European Conference on Radiation and Its Effects on Components and Systems, RADECS 2015. vol. 2015-December, 7365588, Institute of Electrical and Electronics Engineers Inc., 15th European Conference on Radiation and Its Effects on Components and Systems, RADECS 2015, Moscow, Russian Federation, 9/14/15. https://doi.org/10.1109/RADECS.2015.7365588

Gogulamudi AR, Clark LT, Farnsworth C, Chellappa S, Vashishtha V. Architectural and micro-architectural techniques for software controlled microprocessor soft-error mitigation. In 2015 15th European Conference on Radiation and Its Effects on Components and Systems, RADECS 2015. Vol. 2015-December. Institute of Electrical and Electronics Engineers Inc. 2015. 7365588 doi: 10.1109/RADECS.2015.7365588

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abstract = "A MIPS 4Kc compliant embedded microprocessor core design that incorporates architectural features for software controlled radiation upset recovery is presented. The design uses fault tolerance techniques, i.e., error detection and instruction restart, implemented at the micro-Architectural level, with architectural level changes, i.e., new instructions, for error recovery. Fine-grained, self-correcting triple mode redundant circuits protect key architectural state, in addition to dual mode redundancy in the instruction execution pipelines, cache subsystems, and error detection and correction in the register file. The design is implemented in a commercial low standby power 90-nm bulk low standby power CMOS process and the prototype operates at up to 336 MHz.",

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Architectural and micro-architectural techniques for software controlled microprocessor soft-error mitigation

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Keywords

ASJC Scopus subject areas

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