Architectural and micro-architectural techniques for software controlled microprocessor soft-error mitigation

Anudeep R. Gogulamudi, Lawrence T. Clark, Chad Farnsworth, Srivatsan Chellappa, Vinay Vashishtha

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

A MIPS 4Kc compliant embedded microprocessor core design that incorporates architectural features for software controlled radiation upset recovery is presented. The design uses fault tolerance techniques, i.e., error detection and instruction restart, implemented at the micro-Architectural level, with architectural level changes, i.e., new instructions, for error recovery. Fine-grained, self-correcting triple mode redundant circuits protect key architectural state, in addition to dual mode redundancy in the instruction execution pipelines, cache subsystems, and error detection and correction in the register file. The design is implemented in a commercial low standby power 90-nm bulk low standby power CMOS process and the prototype operates at up to 336 MHz.

Original languageEnglish (US)
Title of host publication2015 15th European Conference on Radiation and Its Effects on Components and Systems, RADECS 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
Volume2015-December
ISBN (Electronic)9781509002313
DOIs
StatePublished - Dec 24 2015
Externally publishedYes
Event15th European Conference on Radiation and Its Effects on Components and Systems, RADECS 2015 - Moscow, Russian Federation
Duration: Sep 14 2015Sep 18 2015

Other

Other15th European Conference on Radiation and Its Effects on Components and Systems, RADECS 2015
CountryRussian Federation
CityMoscow
Period9/14/159/18/15

Keywords

  • Microprocessor architecture
  • Radiation hardening
  • Single event effects
  • Soft-errors

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Radiation

Fingerprint Dive into the research topics of 'Architectural and micro-architectural techniques for software controlled microprocessor soft-error mitigation'. Together they form a unique fingerprint.

Cite this