Approximation algorithms for power minimization of earliest deadline first and rate monotonic schedules

Sushu Zhang, Karam S. Chatha, Goran Konjevod

Research output: Chapter in Book/Report/Conference proceedingConference contribution

19 Scopus citations

Abstract

We address power minimization of earliest deadline first and ratemonotonic schedules by voltage and frequency scaling. We prove that the problems are NP-hard, and present (1+ε) fully polynomial time approximation techniques that generate solutions which are guaranteed to be within a specified quality bound (QB=ε) (say within 1% of the optimal). We demonstrate that our techniques can match optimal solutions when QB is set at 1%, out perform existing approaches [1] even when QB is set at 10%, generate solutions that are quite close to optimal (≤ 5%) even when QB is set at higher values (25%), and execute in a fraction of a second (with QB ≥ 5%) for large 100 node task sets.

Original languageEnglish (US)
Title of host publicationISLPED'07
Subtitle of host publicationProceedings of the 2007 International Symposium on Low Power Electronics and Design
Pages225-230
Number of pages6
DOIs
StatePublished - Dec 17 2007
EventISLPED'07: 2007 International Symposium on Low Power Electronics and Design - Portland, OR, United States
Duration: Aug 27 2007Aug 29 2007

Publication series

NameProceedings of the International Symposium on Low Power Electronics and Design
ISSN (Print)1533-4678

Other

OtherISLPED'07: 2007 International Symposium on Low Power Electronics and Design
CountryUnited States
CityPortland, OR
Period8/27/078/29/07

Keywords

  • Earliest deadline first
  • Low power design
  • Rate monotonic

ASJC Scopus subject areas

  • Engineering(all)

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    Zhang, S., Chatha, K. S., & Konjevod, G. (2007). Approximation algorithms for power minimization of earliest deadline first and rate monotonic schedules. In ISLPED'07: Proceedings of the 2007 International Symposium on Low Power Electronics and Design (pp. 225-230). (Proceedings of the International Symposium on Low Power Electronics and Design). https://doi.org/10.1145/1283780.1283828