Approaching optimal characteristics of 10-nm high-performance devices: A quantum transport simulation study of Si FinFET

Hasanur R. Khan; Denis Mamaluy; Dragica Vasileska

doi:10.1109/TED.2007.915387

Approaching optimal characteristics of 10-nm high-performance devices: A quantum transport simulation study of Si FinFET

Hasanur R. Khan, Denis Mamaluy, Dragica Vasileska

Research output: Contribution to journal › Article › peer-review

26 Scopus citations

Abstract

We utilized a fully self-consistent quantum mechanical simulator based on the Contact Block Reduction (CBR) method to optimize a 10 nm FinFET device and meet the International Technology Roadmap for Semiconductors (ITRS) projections for double-gate high-performance logic technology devices. We found that the device ON-current approaching the value projected by the ITRS can be obtained using a conventional unstrained Si channel and a SiO₂ gate insulator. We also performed a detailed analysis of the gate leakage under different bias conditions. Our simulation results show that the quantum mechanical effects significantly enhance the intrinsic switching speed of the device. In our simulations, quantum confinement in both the gates and the channel has been taken into account self-consistently. The obtained theoretical value of the intrinsic switching speed for the considered FinFET device exceeds the ITRS-projected value.

Original language	English (US)
Pages (from-to)	743-753
Number of pages	11
Journal	IEEE Transactions on Electron Devices
Volume	55
Issue number	3
DOIs	https://doi.org/10.1109/TED.2007.915387
State	Published - Mar 2008

Keywords

FinFETs
Gate leakage
Optimized FinFET
Quantum effects
Quantum transport

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

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10.1109/TED.2007.915387

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@article{4e76a5ea9f6045c08e549816f8cd9d2b,

title = "Approaching optimal characteristics of 10-nm high-performance devices: A quantum transport simulation study of Si FinFET",

abstract = "We utilized a fully self-consistent quantum mechanical simulator based on the Contact Block Reduction (CBR) method to optimize a 10 nm FinFET device and meet the International Technology Roadmap for Semiconductors (ITRS) projections for double-gate high-performance logic technology devices. We found that the device ON-current approaching the value projected by the ITRS can be obtained using a conventional unstrained Si channel and a SiO2 gate insulator. We also performed a detailed analysis of the gate leakage under different bias conditions. Our simulation results show that the quantum mechanical effects significantly enhance the intrinsic switching speed of the device. In our simulations, quantum confinement in both the gates and the channel has been taken into account self-consistently. The obtained theoretical value of the intrinsic switching speed for the considered FinFET device exceeds the ITRS-projected value.",

keywords = "FinFETs, Gate leakage, Optimized FinFET, Quantum effects, Quantum transport",

author = "Khan, {Hasanur R.} and Denis Mamaluy and Dragica Vasileska",

note = "Funding Information: Manuscript received October 9, 2007; revised December 4, 2007. This work was supported in part by the Office of Naval Research under Award N000140610094, in part by the National Science Foundation, and in part by the Arizona Institute of Nano-Electronics (AINE). The review of this paper was arranged by Editor S. Datta The authors are with the Department of Electrical Engineering, Arizona State University, Tempe, AZ 85287 USA (e-mail: hrkhan@asu.edu; mamaluy@asu.edu).",

year = "2008",

month = mar,

doi = "10.1109/TED.2007.915387",

language = "English (US)",

volume = "55",

pages = "743--753",

journal = "IEEE Transactions on Electron Devices",

issn = "0018-9383",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "3",

}

TY - JOUR

T1 - Approaching optimal characteristics of 10-nm high-performance devices

T2 - A quantum transport simulation study of Si FinFET

AU - Khan, Hasanur R.

AU - Mamaluy, Denis

AU - Vasileska, Dragica

N1 - Funding Information: Manuscript received October 9, 2007; revised December 4, 2007. This work was supported in part by the Office of Naval Research under Award N000140610094, in part by the National Science Foundation, and in part by the Arizona Institute of Nano-Electronics (AINE). The review of this paper was arranged by Editor S. Datta The authors are with the Department of Electrical Engineering, Arizona State University, Tempe, AZ 85287 USA (e-mail: hrkhan@asu.edu; mamaluy@asu.edu).

PY - 2008/3

Y1 - 2008/3

N2 - We utilized a fully self-consistent quantum mechanical simulator based on the Contact Block Reduction (CBR) method to optimize a 10 nm FinFET device and meet the International Technology Roadmap for Semiconductors (ITRS) projections for double-gate high-performance logic technology devices. We found that the device ON-current approaching the value projected by the ITRS can be obtained using a conventional unstrained Si channel and a SiO2 gate insulator. We also performed a detailed analysis of the gate leakage under different bias conditions. Our simulation results show that the quantum mechanical effects significantly enhance the intrinsic switching speed of the device. In our simulations, quantum confinement in both the gates and the channel has been taken into account self-consistently. The obtained theoretical value of the intrinsic switching speed for the considered FinFET device exceeds the ITRS-projected value.

AB - We utilized a fully self-consistent quantum mechanical simulator based on the Contact Block Reduction (CBR) method to optimize a 10 nm FinFET device and meet the International Technology Roadmap for Semiconductors (ITRS) projections for double-gate high-performance logic technology devices. We found that the device ON-current approaching the value projected by the ITRS can be obtained using a conventional unstrained Si channel and a SiO2 gate insulator. We also performed a detailed analysis of the gate leakage under different bias conditions. Our simulation results show that the quantum mechanical effects significantly enhance the intrinsic switching speed of the device. In our simulations, quantum confinement in both the gates and the channel has been taken into account self-consistently. The obtained theoretical value of the intrinsic switching speed for the considered FinFET device exceeds the ITRS-projected value.

KW - FinFETs

KW - Gate leakage

KW - Optimized FinFET

KW - Quantum effects

KW - Quantum transport

UR - http://www.scopus.com/inward/record.url?scp=40949100956&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=40949100956&partnerID=8YFLogxK

U2 - 10.1109/TED.2007.915387

DO - 10.1109/TED.2007.915387

M3 - Article

AN - SCOPUS:40949100956

SN - 0018-9383

VL - 55

SP - 743

EP - 753

JO - IEEE Transactions on Electron Devices

JF - IEEE Transactions on Electron Devices

IS - 3

ER -

Approaching optimal characteristics of 10-nm high-performance devices: A quantum transport simulation study of Si FinFET

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