Applying architectural vulnerability analysis to hard faults in the microprocessor

Fred A. Bower, Derek Hower, Mahmut Yilmaz, Daniel J. Sorin, Sule Ozev

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Scopus citations

Abstract

In this paper, we present a new metric, Hard-Fault Architectural Vulnerability Factor (H-AVF), to allow designers to more effectively compare alternate hard-fault tolerance schemes. In order to provide intuition on the use of H-AVF as a metric, we evaluate fault-tolerant level-1 data cache and register file implementations using error correcting codes and a fault-tolerant adder using triple-modular redundancy (TMR). For each of the designs, we compute its H-AVF. We then use these H-AVF values in conjunction with other properties of the design, such as die area and power consumption, to provide composite metrics. The derived metrics provide simple, quantitative measures of the cost-effectiveness of the evaluated designs.

Original languageEnglish (US)
Title of host publicationSIGMETRICS 2006/Performance 2006 - Joint International Conference on Measurement and Modeling of Computer Systems, Proceedings
Pages375-376
Number of pages2
Edition1
DOIs
StatePublished - Jun 2006
Externally publishedYes
EventSIGMETRICS 2006/Performance 2006 - Joint International Conference on Measurement and Modeling of Computer Systems - Saint Malo, France
Duration: Jun 26 2006Jun 30 2006

Publication series

NamePerformance Evaluation Review
Number1
Volume34
ISSN (Print)0163-5999
ISSN (Electronic)0163-5999

Other

OtherSIGMETRICS 2006/Performance 2006 - Joint International Conference on Measurement and Modeling of Computer Systems
Country/TerritoryFrance
CitySaint Malo
Period6/26/066/30/06

Keywords

  • Computer architecture
  • Hard-fault tolerance
  • Reliability

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Computer Networks and Communications

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