Applying architectural vulnerability analysis to hard faults in the microprocessor

Fred A. Bower, Derek Hower, Mahmut Yilmaz, Daniel J. Sorin, Sule Ozev

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

In this paper, we present a new metric, Hard-Fault Architectural Vulnerability Factor (H-AVF), to allow designers to more effectively compare alternate hard-fault tolerance schemes. In order to provide intuition on the use of H-AVF as a metric, we evaluate fault-tolerant level-1 data cache and register file implementations using error correcting codes and a fault-tolerant adder using triple-modular redundancy (TMR). For each of the designs, we compute its H-AVF. We then use these H-AVF values in conjunction with other properties of the design, such as die area and power consumption, to provide composite metrics. The derived metrics provide simple, quantitative measures of the cost-effectiveness of the evaluated designs.

Original languageEnglish (US)
Title of host publicationPerformance Evaluation Review
Pages375-376
Number of pages2
Volume34
Edition1
DOIs
StatePublished - Jun 2006
Externally publishedYes
EventSIGMETRICS 2006/Performance 2006 - Joint International Conference on Measurement and Modeling of Computer Systems - Saint Malo, France
Duration: Jun 26 2006Jun 30 2006

Other

OtherSIGMETRICS 2006/Performance 2006 - Joint International Conference on Measurement and Modeling of Computer Systems
CountryFrance
CitySaint Malo
Period6/26/066/30/06

Fingerprint

Microprocessor chips
Adders
Cost effectiveness
Fault tolerance
Redundancy
Electric power utilization
Composite materials

Keywords

  • Computer architecture
  • Hard-fault tolerance
  • Reliability

ASJC Scopus subject areas

  • Hardware and Architecture

Cite this

Bower, F. A., Hower, D., Yilmaz, M., Sorin, D. J., & Ozev, S. (2006). Applying architectural vulnerability analysis to hard faults in the microprocessor. In Performance Evaluation Review (1 ed., Vol. 34, pp. 375-376) https://doi.org/10.1145/1140103.1140327

Applying architectural vulnerability analysis to hard faults in the microprocessor. / Bower, Fred A.; Hower, Derek; Yilmaz, Mahmut; Sorin, Daniel J.; Ozev, Sule.

Performance Evaluation Review. Vol. 34 1. ed. 2006. p. 375-376.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Bower, FA, Hower, D, Yilmaz, M, Sorin, DJ & Ozev, S 2006, Applying architectural vulnerability analysis to hard faults in the microprocessor. in Performance Evaluation Review. 1 edn, vol. 34, pp. 375-376, SIGMETRICS 2006/Performance 2006 - Joint International Conference on Measurement and Modeling of Computer Systems, Saint Malo, France, 6/26/06. https://doi.org/10.1145/1140103.1140327
Bower FA, Hower D, Yilmaz M, Sorin DJ, Ozev S. Applying architectural vulnerability analysis to hard faults in the microprocessor. In Performance Evaluation Review. 1 ed. Vol. 34. 2006. p. 375-376 https://doi.org/10.1145/1140103.1140327
Bower, Fred A. ; Hower, Derek ; Yilmaz, Mahmut ; Sorin, Daniel J. ; Ozev, Sule. / Applying architectural vulnerability analysis to hard faults in the microprocessor. Performance Evaluation Review. Vol. 34 1. ed. 2006. pp. 375-376
@inproceedings{b72ebfd2ad7c4887a5263618e5c7f5b4,
title = "Applying architectural vulnerability analysis to hard faults in the microprocessor",
abstract = "In this paper, we present a new metric, Hard-Fault Architectural Vulnerability Factor (H-AVF), to allow designers to more effectively compare alternate hard-fault tolerance schemes. In order to provide intuition on the use of H-AVF as a metric, we evaluate fault-tolerant level-1 data cache and register file implementations using error correcting codes and a fault-tolerant adder using triple-modular redundancy (TMR). For each of the designs, we compute its H-AVF. We then use these H-AVF values in conjunction with other properties of the design, such as die area and power consumption, to provide composite metrics. The derived metrics provide simple, quantitative measures of the cost-effectiveness of the evaluated designs.",
keywords = "Computer architecture, Hard-fault tolerance, Reliability",
author = "Bower, {Fred A.} and Derek Hower and Mahmut Yilmaz and Sorin, {Daniel J.} and Sule Ozev",
year = "2006",
month = "6",
doi = "10.1145/1140103.1140327",
language = "English (US)",
isbn = "1595933204",
volume = "34",
pages = "375--376",
booktitle = "Performance Evaluation Review",
edition = "1",

}

TY - GEN

T1 - Applying architectural vulnerability analysis to hard faults in the microprocessor

AU - Bower, Fred A.

AU - Hower, Derek

AU - Yilmaz, Mahmut

AU - Sorin, Daniel J.

AU - Ozev, Sule

PY - 2006/6

Y1 - 2006/6

N2 - In this paper, we present a new metric, Hard-Fault Architectural Vulnerability Factor (H-AVF), to allow designers to more effectively compare alternate hard-fault tolerance schemes. In order to provide intuition on the use of H-AVF as a metric, we evaluate fault-tolerant level-1 data cache and register file implementations using error correcting codes and a fault-tolerant adder using triple-modular redundancy (TMR). For each of the designs, we compute its H-AVF. We then use these H-AVF values in conjunction with other properties of the design, such as die area and power consumption, to provide composite metrics. The derived metrics provide simple, quantitative measures of the cost-effectiveness of the evaluated designs.

AB - In this paper, we present a new metric, Hard-Fault Architectural Vulnerability Factor (H-AVF), to allow designers to more effectively compare alternate hard-fault tolerance schemes. In order to provide intuition on the use of H-AVF as a metric, we evaluate fault-tolerant level-1 data cache and register file implementations using error correcting codes and a fault-tolerant adder using triple-modular redundancy (TMR). For each of the designs, we compute its H-AVF. We then use these H-AVF values in conjunction with other properties of the design, such as die area and power consumption, to provide composite metrics. The derived metrics provide simple, quantitative measures of the cost-effectiveness of the evaluated designs.

KW - Computer architecture

KW - Hard-fault tolerance

KW - Reliability

UR - http://www.scopus.com/inward/record.url?scp=33750367419&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=33750367419&partnerID=8YFLogxK

U2 - 10.1145/1140103.1140327

DO - 10.1145/1140103.1140327

M3 - Conference contribution

AN - SCOPUS:33750367419

SN - 1595933204

SN - 9781595933201

VL - 34

SP - 375

EP - 376

BT - Performance Evaluation Review

ER -