AnySP: Anytime anywhere anyway signal processing

Mark Woh, Sangwon Seo, Scott Mahlke, Trevor Mudge, Chaitali Chakrabarti, Krisztian Flautner

Research output: Chapter in Book/Report/Conference proceedingConference contribution

72 Scopus citations


In the past decade, the proliferation of mobile devices has increased at a spectacular rate. There are now more than 3.3 billion active cell phones in the world - a device that we now all depend on in our daily lives. The current generation of devices employs a combination of general-purpose processors, digital signal processors, and hardwired accelerators to provide giga-operations-per-second performance on milliWatt power budgets. Such heterogeneous organizations are inefficient to build and maintain, as well as waste silicon area and power. Looking forward to the next generation of mobile computing, computation requirements will increase by one to three orders of magnitude due to higher data rates, increased complexity algorithms, and greater computation diversity but the power requirements will be just as stringent. Scaling of existing approaches will not suffice instead the inherent computational efficiency, programma-bility, and adaptability of the hardware must change. To overcome these challenges, this paper proposes an example architecture, referred to as AnySP, for the next generation mobile signal processing. AnySP uses a co-design approach where the next generation wireless signal processing and high-definition video algorithms are analyzed to create a domain specific programmable architecture. At the heart of AnySP is a configurable single-instruction multiple-data datapath that is capable of processing wide vectors or multiple narrow vectors simultaneously. In addition, deeper computation subgraphs can be pipelined across the single-instruction multiple-data lanes. These three operating modes provide high throughput across varying application types. Results show that AnySP is capable of sustaining 4G wireless processing and high-definition video throughput rates, and will approach the 1000 Mops/mW efficiency barrier when scaled to 45nm.

Original languageEnglish (US)
Title of host publicationISCA 2009 - 36th Annual International Symposium on Computer Architecture, Conference Proceedings
Number of pages12
StatePublished - 2009
EventISCA 2009 - 36th Annual International Symposium on Computer Architecture - Austin, TX, United States
Duration: Jun 20 2009Jun 24 2009

Publication series

NameProceedings - International Symposium on Computer Architecture
ISSN (Print)1063-6897


OtherISCA 2009 - 36th Annual International Symposium on Computer Architecture
Country/TerritoryUnited States
CityAustin, TX


  • Algorithms
  • Design
  • Performance

ASJC Scopus subject areas

  • Hardware and Architecture


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