In this work, we investigate the robustness of 1-transistor-1-resistor (1T1R) synaptic array to implement a low-precision neural network. The experimental results on 1 kb HfOx-based RRAM array show a large on/off ratio (i.e. > 105×) and 5 stable resistance states can be reliably achieved with 10× window between adjacent two states. As the RRAM has the resistance drift over time under read voltage stress, the impact of read disturbance occurred in 1T1R synaptic array on the neural network classification accuracy is analyzed with the RRAM compact model fitted with experimental data. The simulation results of a single-layer perceptron with compressed MNIST dataset indicate that 1) more stable multi-level states are desired to have higher mapping capability of weights, thus achieving a higher initial classification accuracy; 2) good mapping strategies that avoid the read disturbance-induced sign change on the most significant weight levels are very important to mitigate the classification accuracy loss.