Analysis of SEGR in Silicon Planar Gate Super-Junction Power MOSFETs

K. Muthuseenu, H. J. Barnaby, K. F. Galloway, A. E. Koziukov, T. A. Maksimenko, M. Y. Vyrostkov, K. B. Bu-Khasan, A. A. Kalashnikova, A. Privat

Research output: Contribution to journalArticlepeer-review

Abstract

This article compares and analyzes the single-event gate rupture (SEGR) response of silicon planar gate super-junction (SJ) power metal oxide semiconductor field effect transistors (MOSFETs) and vertical double diffused power MOSFETs (VDMOSs). When an incident heavy-ion strike is perpendicular to the gate oxide, the SEGR tolerances of SJ power MOSFETs (SJMOSs) and VDMOSs are similar. But, for heavy-ion strikes that are at different angles, SJMOS has better SEGR tolerance than VDMOS. This improved performance of SJMOS is due to the presence of an additional horizontal electric field component in SJMOS devices. This is validated using the experimental data and simulation results in this article.

Original languageEnglish (US)
Article number9328811
Pages (from-to)611-616
Number of pages6
JournalIEEE Transactions on Nuclear Science
Volume68
Issue number5
DOIs
StatePublished - May 2021
Externally publishedYes

Keywords

  • Heavy ion
  • VDMOS
  • power MOSFET
  • single-event gate rupture (SEGR)
  • super-junction (SJ)
  • technology computer-aided design (TCAD) analysis

ASJC Scopus subject areas

  • Nuclear and High Energy Physics
  • Nuclear Energy and Engineering
  • Electrical and Electronic Engineering

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