Circuit reliability is an increasingly important concern. Most of the reliability studies have concentrated on digital circuits, which have typically led analog circuits in terms of technology node. This is no longer true as both RF/analog and digital components are being integrated with the leading edge manufacturing process. In this paper, we present a methodology for analyzing the parametric degradation caused by electro migration in inductors and vias at design time. We identify reliability hot spots and concentrate our efforts on these circuit components to enhance the lifetime of the circuit with low area and no performance impact.