An ultra-low-power memory with a subthreshold power supply voltage

Jinhui Chen, Lawrence T. Clark, Tai Hua Chen

Research output: Contribution to journalArticle

70 Scopus citations

Abstract

A 512 × 13 bit ultra-low-power subthreshold memory is fabricated on a 130-nm process technology. The fabricated memory is fully functional for read operation with a 190-mV power supply at 28 kHz, and 216 mV for write operation. Single bits are measured to read and write properly with V DD as low as 103 mV and 129 mV, respectively. The memory operates at a 1-MHz clock rate with a 310-mV power supply. This operating point has 1.197 μW power consumption, of which 0.366 μW is due to leakage and 0.831 μW is due to dynamic power dissipation. Analysis of the available fan-out or fan-in that can be supported at a given voltage is summarized. A number of circuit techniques are presented to overcome the substantially reduced on-to-off current ratios and the poor drive strength of transistors operating in subthreshold. These include a gated feedback memory cell, and hierarchical read and decode circuits. The memory is dynamic, with pseudo-static operation provided via self-timed control of the keeper transistors to mitigate increased variability manifested in subthreshold operation.

Original languageEnglish (US)
Article number1703689
Pages (from-to)2344-2353
Number of pages10
JournalIEEE Journal of Solid-State Circuits
Volume41
Issue number10
DOIs
StatePublished - Oct 1 2006

Keywords

  • High fan-in/out
  • On-to-off current ratio
  • Subthreshold memory
  • Ultra-low power

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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