TY - GEN
T1 - An optimal analytical solution for processor speed control with thermal constraints
AU - Rao, Ravishankar
AU - Vrudhula, Sarma
AU - Chakrabarti, Chaitali
AU - Chang, Naehyuck
PY - 2006/12/1
Y1 - 2006/12/1
N2 - As semiconductor manufacturing technology scales to smaller device sizes, the power consumption of clocked digital ICs begins to increase. Dynamic voltage and frequency scaling (DVFS) is a well-known technique for conserving energy. Recently, it has also been used to control the CPU temperature as part of Dynamic Thermal Management (DTM) techniques. Most works in these areas assume that the optimum speed profile (for either minimizing energy or maximizing performance) is a constant profile. However, in the presence of thermal constraints, we show that the optimal profile is in general, a time-varying function. We formulate the problem of maximizing the average throughput of a processor over a given time period, subject to thermal and speed constraints, as a problem in the calculus of variations. The variational approach provides a powerful framework for precisely specifying and solving the speed control problem, and allows us to obtain an exact analytical solution. The solution methodology is very general, and works for any convex power model, and simple lumped RC thermal models. The resulting speed profiles were found to consist of up to three segments, of which one of them is a decreasing function of time, and the others are constant. We analyze the effect of different parameters like the initial temperature, thermal capacitance and the maximum rated speed on the nature and the cost of the optimum solution. We also propose a two-speed solution that approximates the optimal speed curve. This solution was found to achieve a performance close to that of the optimum, and is also easier to implement in real processors.
AB - As semiconductor manufacturing technology scales to smaller device sizes, the power consumption of clocked digital ICs begins to increase. Dynamic voltage and frequency scaling (DVFS) is a well-known technique for conserving energy. Recently, it has also been used to control the CPU temperature as part of Dynamic Thermal Management (DTM) techniques. Most works in these areas assume that the optimum speed profile (for either minimizing energy or maximizing performance) is a constant profile. However, in the presence of thermal constraints, we show that the optimal profile is in general, a time-varying function. We formulate the problem of maximizing the average throughput of a processor over a given time period, subject to thermal and speed constraints, as a problem in the calculus of variations. The variational approach provides a powerful framework for precisely specifying and solving the speed control problem, and allows us to obtain an exact analytical solution. The solution methodology is very general, and works for any convex power model, and simple lumped RC thermal models. The resulting speed profiles were found to consist of up to three segments, of which one of them is a decreasing function of time, and the others are constant. We analyze the effect of different parameters like the initial temperature, thermal capacitance and the maximum rated speed on the nature and the cost of the optimum solution. We also propose a two-speed solution that approximates the optimal speed curve. This solution was found to achieve a performance close to that of the optimum, and is also easier to implement in real processors.
KW - DIM
KW - DVFS
KW - Optimal control
KW - Temperature
KW - Thermal management
UR - http://www.scopus.com/inward/record.url?scp=34247249821&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=34247249821&partnerID=8YFLogxK
U2 - 10.1145/1165573.1165643
DO - 10.1145/1165573.1165643
M3 - Conference contribution
AN - SCOPUS:34247249821
SN - 1595934626
SN - 9781595934628
T3 - Proceedings of the International Symposium on Low Power Electronics and Design
SP - 292
EP - 297
BT - ISLPED'06 - Proceedings of the 2006 International Symposium on Low Power Electronics and Design
T2 - ISLPED'06 - 11th ACM/IEEE International Symposium on Low Power Electronics and Design
Y2 - 4 October 2006 through 6 October 2006
ER -