An On-Chip Learning Accelerator for Spiking Neural Networks using STT-RAM Crossbar Arrays

Shruti R. Kulkarni, Shihui Yin, Jae Sun Seo, Bipin Rajendran

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this work, we present a scheme for implementing learning on a digital non-volatile memory (NVM) based hardware accelerator for Spiking Neural Networks (SNNs). Our design estimates across three prominent non-volatile memories - Phase Change Memory (PCM), Resistive RAM (RRAM), and Spin Transfer Torque RAM (STT-RAM) show that the STT-RAM arrays enable at least 2× higher throughput compared to the other two memory technologies. We discuss the design and the signal communication framework through the STT-RAM crossbar array for training and inference in SNNs. Each STT-RAM cell in the array stores a single bit value. Our neurosynaptic computational core consists of the memory crossbar array and its read/write peripheral circuitry and the digital logic for the spiking neurons, weight update computations, spike router, and decoder for incoming spike packets. Our STT-RAM based design shows ~20× higher performance per unit Watt per unit area compared to conventional SRAM based design, making it a promising learning platform for realizing systems with significant area and power limitations.

Original languageEnglish (US)
Title of host publicationProceedings of the 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020
EditorsGiorgio Di Natale, Cristiana Bolchini, Elena-Ioana Vatajelu
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1019-1024
Number of pages6
ISBN (Electronic)9783981926347
DOIs
StatePublished - Mar 2020
Event2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020 - Grenoble, France
Duration: Mar 9 2020Mar 13 2020

Publication series

NameProceedings of the 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020

Conference

Conference2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020
CountryFrance
CityGrenoble
Period3/9/203/13/20

Keywords

  • crossbar arrays
  • Neuromorphic hardware
  • Spiking Neural Networks
  • STT-RAM

ASJC Scopus subject areas

  • Hardware and Architecture
  • Safety, Risk, Reliability and Quality
  • Modeling and Simulation
  • Electrical and Electronic Engineering

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  • Cite this

    Kulkarni, S. R., Yin, S., Seo, J. S., & Rajendran, B. (2020). An On-Chip Learning Accelerator for Spiking Neural Networks using STT-RAM Crossbar Arrays. In G. Di Natale, C. Bolchini, & E-I. Vatajelu (Eds.), Proceedings of the 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020 (pp. 1019-1024). [9116226] (Proceedings of the 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.23919/DATE48585.2020.9116226