An Integrated Modeling Paradigm of Circuit Reliability for 65nm CMOS Technology

Wenping Wang; Vijay Reddy; Anand T. Krishnan; Rakesh Vattikonda; Srikanth Krishnan; Yu Cao

doi:10.1109/CICC.2007.4405783

An Integrated Modeling Paradigm of Circuit Reliability for 65nm CMOS Technology

Wenping Wang, Vijay Reddy, Anand T. Krishnan, Rakesh Vattikonda, Srikanth Krishnan, Yu Cao

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

19 Scopus citations

Abstract

The de facto modeling method to analyze channel-hot-carrier (CHC) is based on substrate current (I_sub), which becomes increasingly problematic with technology scaling as various leakage components dominate I_sub. In this work, we present a unified approach that directly predicts the change of key transistor parameters under various process and design conditions, for both negative-bias-temperature-instability (NBTI) and CHC degradation. Using the general reaction-diffusion model and the concept of surface potential, the proposed method continuously captures the performance degradation across subthreshold and strong inversion regions. Models are comprehensively verified with an industrial 65nm technology. We benchmark the prediction of circuit performance degradation with measured ring oscillator data and simulations of an amplifier.

Original language	English (US)
Title of host publication	Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	511-514
Number of pages	4
ISBN (Electronic)	1424407869, 9781424407866
DOIs	https://doi.org/10.1109/CICC.2007.4405783
State	Published - 2007
Event	29th Annual IEEE Custom Integrated Circuits Conference, CICC 2007 - San Jose, United States Duration: Sep 16 2007 → Sep 19 2007

Publication series

Name	Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007

Other

Other	29th Annual IEEE Custom Integrated Circuits Conference, CICC 2007
Country/Territory	United States
City	San Jose
Period	9/16/07 → 9/19/07

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/CICC.2007.4405783

Cite this

Wang, W., Reddy, V., Krishnan, A. T., Vattikonda, R., Krishnan, S., & Cao, Y. (2007). An Integrated Modeling Paradigm of Circuit Reliability for 65nm CMOS Technology. In Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007 (pp. 511-514). [4405783] (Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CICC.2007.4405783

An Integrated Modeling Paradigm of Circuit Reliability for 65nm CMOS Technology. / Wang, Wenping; Reddy, Vijay; Krishnan, Anand T.; Vattikonda, Rakesh; Krishnan, Srikanth; Cao, Yu.

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007. Institute of Electrical and Electronics Engineers Inc., 2007. p. 511-514 4405783 (Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Wang, W, Reddy, V, Krishnan, AT, Vattikonda, R, Krishnan, S & Cao, Y 2007, An Integrated Modeling Paradigm of Circuit Reliability for 65nm CMOS Technology. in Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007., 4405783, Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007, Institute of Electrical and Electronics Engineers Inc., pp. 511-514, 29th Annual IEEE Custom Integrated Circuits Conference, CICC 2007, San Jose, United States, 9/16/07. https://doi.org/10.1109/CICC.2007.4405783

Wang W, Reddy V, Krishnan AT, Vattikonda R, Krishnan S, Cao Y. An Integrated Modeling Paradigm of Circuit Reliability for 65nm CMOS Technology. In Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007. Institute of Electrical and Electronics Engineers Inc. 2007. p. 511-514. 4405783. (Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007). https://doi.org/10.1109/CICC.2007.4405783

Wang, Wenping ; Reddy, Vijay ; Krishnan, Anand T. ; Vattikonda, Rakesh ; Krishnan, Srikanth ; Cao, Yu. / An Integrated Modeling Paradigm of Circuit Reliability for 65nm CMOS Technology. Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007. Institute of Electrical and Electronics Engineers Inc., 2007. pp. 511-514 (Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007).

@inproceedings{9c0c9dc5d6904b9189f68c949e9270bd,

title = "An Integrated Modeling Paradigm of Circuit Reliability for 65nm CMOS Technology",

abstract = "The de facto modeling method to analyze channel-hot-carrier (CHC) is based on substrate current (Isub), which becomes increasingly problematic with technology scaling as various leakage components dominate Isub. In this work, we present a unified approach that directly predicts the change of key transistor parameters under various process and design conditions, for both negative-bias-temperature-instability (NBTI) and CHC degradation. Using the general reaction-diffusion model and the concept of surface potential, the proposed method continuously captures the performance degradation across subthreshold and strong inversion regions. Models are comprehensively verified with an industrial 65nm technology. We benchmark the prediction of circuit performance degradation with measured ring oscillator data and simulations of an amplifier.",

author = "Wenping Wang and Vijay Reddy and Krishnan, {Anand T.} and Rakesh Vattikonda and Srikanth Krishnan and Yu Cao",

note = "Publisher Copyright: {\textcopyright} 2007 IEEE. Copyright: Copyright 2015 Elsevier B.V., All rights reserved.; 29th Annual IEEE Custom Integrated Circuits Conference, CICC 2007 ; Conference date: 16-09-2007 Through 19-09-2007",

year = "2007",

doi = "10.1109/CICC.2007.4405783",

language = "English (US)",

series = "Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "511--514",

booktitle = "Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007",

}

TY - GEN

T1 - An Integrated Modeling Paradigm of Circuit Reliability for 65nm CMOS Technology

AU - Wang, Wenping

AU - Reddy, Vijay

AU - Krishnan, Anand T.

AU - Vattikonda, Rakesh

AU - Krishnan, Srikanth

AU - Cao, Yu

PY - 2007

Y1 - 2007

N2 - The de facto modeling method to analyze channel-hot-carrier (CHC) is based on substrate current (Isub), which becomes increasingly problematic with technology scaling as various leakage components dominate Isub. In this work, we present a unified approach that directly predicts the change of key transistor parameters under various process and design conditions, for both negative-bias-temperature-instability (NBTI) and CHC degradation. Using the general reaction-diffusion model and the concept of surface potential, the proposed method continuously captures the performance degradation across subthreshold and strong inversion regions. Models are comprehensively verified with an industrial 65nm technology. We benchmark the prediction of circuit performance degradation with measured ring oscillator data and simulations of an amplifier.

AB - The de facto modeling method to analyze channel-hot-carrier (CHC) is based on substrate current (Isub), which becomes increasingly problematic with technology scaling as various leakage components dominate Isub. In this work, we present a unified approach that directly predicts the change of key transistor parameters under various process and design conditions, for both negative-bias-temperature-instability (NBTI) and CHC degradation. Using the general reaction-diffusion model and the concept of surface potential, the proposed method continuously captures the performance degradation across subthreshold and strong inversion regions. Models are comprehensively verified with an industrial 65nm technology. We benchmark the prediction of circuit performance degradation with measured ring oscillator data and simulations of an amplifier.

UR - http://www.scopus.com/inward/record.url?scp=84938602082&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84938602082&partnerID=8YFLogxK

U2 - 10.1109/CICC.2007.4405783

DO - 10.1109/CICC.2007.4405783

M3 - Conference contribution

AN - SCOPUS:84938602082

T3 - Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007

SP - 511

EP - 514

BT - Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 29th Annual IEEE Custom Integrated Circuits Conference, CICC 2007

Y2 - 16 September 2007 through 19 September 2007

ER -

An Integrated Modeling Paradigm of Circuit Reliability for 65nm CMOS Technology

Abstract

Publication series

Other

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this