TY - GEN
T1 - An Integrated Modeling Paradigm of Circuit Reliability for 65nm CMOS Technology
AU - Wang, Wenping
AU - Reddy, Vijay
AU - Krishnan, Anand T.
AU - Vattikonda, Rakesh
AU - Krishnan, Srikanth
AU - Cao, Yu
N1 - Publisher Copyright:
© 2007 IEEE.
Copyright:
Copyright 2015 Elsevier B.V., All rights reserved.
PY - 2007
Y1 - 2007
N2 - The de facto modeling method to analyze channel-hot-carrier (CHC) is based on substrate current (Isub), which becomes increasingly problematic with technology scaling as various leakage components dominate Isub. In this work, we present a unified approach that directly predicts the change of key transistor parameters under various process and design conditions, for both negative-bias-temperature-instability (NBTI) and CHC degradation. Using the general reaction-diffusion model and the concept of surface potential, the proposed method continuously captures the performance degradation across subthreshold and strong inversion regions. Models are comprehensively verified with an industrial 65nm technology. We benchmark the prediction of circuit performance degradation with measured ring oscillator data and simulations of an amplifier.
AB - The de facto modeling method to analyze channel-hot-carrier (CHC) is based on substrate current (Isub), which becomes increasingly problematic with technology scaling as various leakage components dominate Isub. In this work, we present a unified approach that directly predicts the change of key transistor parameters under various process and design conditions, for both negative-bias-temperature-instability (NBTI) and CHC degradation. Using the general reaction-diffusion model and the concept of surface potential, the proposed method continuously captures the performance degradation across subthreshold and strong inversion regions. Models are comprehensively verified with an industrial 65nm technology. We benchmark the prediction of circuit performance degradation with measured ring oscillator data and simulations of an amplifier.
UR - http://www.scopus.com/inward/record.url?scp=84938602082&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84938602082&partnerID=8YFLogxK
U2 - 10.1109/CICC.2007.4405783
DO - 10.1109/CICC.2007.4405783
M3 - Conference contribution
AN - SCOPUS:84938602082
T3 - Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007
SP - 511
EP - 514
BT - Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 29th Annual IEEE Custom Integrated Circuits Conference, CICC 2007
Y2 - 16 September 2007 through 19 September 2007
ER -