An Integrated Modeling Paradigm of Circuit Reliability for 65nm CMOS Technology

Wenping Wang, Vijay Reddy, Anand T. Krishnan, Rakesh Vattikonda, Srikanth Krishnan, Yu Cao

Research output: Chapter in Book/Report/Conference proceedingConference contribution

18 Scopus citations

Abstract

The de facto modeling method to analyze channel-hot-carrier (CHC) is based on substrate current (Isub), which becomes increasingly problematic with technology scaling as various leakage components dominate Isub. In this work, we present a unified approach that directly predicts the change of key transistor parameters under various process and design conditions, for both negative-bias-temperature-instability (NBTI) and CHC degradation. Using the general reaction-diffusion model and the concept of surface potential, the proposed method continuously captures the performance degradation across subthreshold and strong inversion regions. Models are comprehensively verified with an industrial 65nm technology. We benchmark the prediction of circuit performance degradation with measured ring oscillator data and simulations of an amplifier.

Original languageEnglish (US)
Title of host publicationProceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages511-514
Number of pages4
ISBN (Electronic)1424407869, 9781424407866
DOIs
StatePublished - 2007
Event29th Annual IEEE Custom Integrated Circuits Conference, CICC 2007 - San Jose, United States
Duration: Sep 16 2007Sep 19 2007

Publication series

NameProceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007

Other

Other29th Annual IEEE Custom Integrated Circuits Conference, CICC 2007
CountryUnited States
CitySan Jose
Period9/16/079/19/07

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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