An Integrated Modeling Paradigm of Circuit Reliability for 65nm CMOS Technology

Wenping Wang; Vijay Reddy; Anand T. Krishnan; Rakesh Vattikonda; Srikanth Krishnan; Yu Cao

doi:10.1109/CICC.2007.4405783

An Integrated Modeling Paradigm of Circuit Reliability for 65nm CMOS Technology

Wenping Wang, Vijay Reddy, Anand T. Krishnan, Rakesh Vattikonda, Srikanth Krishnan, Yu Cao

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

19 Scopus citations

Abstract

The de facto modeling method to analyze channel-hot-carrier (CHC) is based on substrate current (I_sub), which becomes increasingly problematic with technology scaling as various leakage components dominate I_sub. In this work, we present a unified approach that directly predicts the change of key transistor parameters under various process and design conditions, for both negative-bias-temperature-instability (NBTI) and CHC degradation. Using the general reaction-diffusion model and the concept of surface potential, the proposed method continuously captures the performance degradation across subthreshold and strong inversion regions. Models are comprehensively verified with an industrial 65nm technology. We benchmark the prediction of circuit performance degradation with measured ring oscillator data and simulations of an amplifier.

Original language	English (US)
Title of host publication	Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	511-514
Number of pages	4
ISBN (Electronic)	1424407869, 9781424407866
DOIs	https://doi.org/10.1109/CICC.2007.4405783
State	Published - 2007
Event	29th Annual IEEE Custom Integrated Circuits Conference, CICC 2007 - San Jose, United States Duration: Sep 16 2007 → Sep 19 2007

Publication series

Name	Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007

Other

Other	29th Annual IEEE Custom Integrated Circuits Conference, CICC 2007
Country/Territory	United States
City	San Jose
Period	9/16/07 → 9/19/07

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/CICC.2007.4405783

Cite this

Wang, W., Reddy, V., Krishnan, A. T., Vattikonda, R., Krishnan, S., & Cao, Y. (2007). An Integrated Modeling Paradigm of Circuit Reliability for 65nm CMOS Technology. In Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007 (pp. 511-514). [4405783] (Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CICC.2007.4405783

An Integrated Modeling Paradigm of Circuit Reliability for 65nm CMOS Technology. / Wang, Wenping; Reddy, Vijay; Krishnan, Anand T. et al.

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007. Institute of Electrical and Electronics Engineers Inc., 2007. p. 511-514 4405783 (Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Wang, W, Reddy, V, Krishnan, AT, Vattikonda, R, Krishnan, S & Cao, Y 2007, An Integrated Modeling Paradigm of Circuit Reliability for 65nm CMOS Technology. in Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007., 4405783, Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007, Institute of Electrical and Electronics Engineers Inc., pp. 511-514, 29th Annual IEEE Custom Integrated Circuits Conference, CICC 2007, San Jose, United States, 9/16/07. https://doi.org/10.1109/CICC.2007.4405783

Wang W, Reddy V, Krishnan AT, Vattikonda R, Krishnan S, Cao Y. An Integrated Modeling Paradigm of Circuit Reliability for 65nm CMOS Technology. In Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007. Institute of Electrical and Electronics Engineers Inc. 2007. p. 511-514. 4405783. (Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007). doi: 10.1109/CICC.2007.4405783

Wang, Wenping ; Reddy, Vijay ; Krishnan, Anand T. et al. / An Integrated Modeling Paradigm of Circuit Reliability for 65nm CMOS Technology. Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007. Institute of Electrical and Electronics Engineers Inc., 2007. pp. 511-514 (Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007).

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abstract = "The de facto modeling method to analyze channel-hot-carrier (CHC) is based on substrate current (Isub), which becomes increasingly problematic with technology scaling as various leakage components dominate Isub. In this work, we present a unified approach that directly predicts the change of key transistor parameters under various process and design conditions, for both negative-bias-temperature-instability (NBTI) and CHC degradation. Using the general reaction-diffusion model and the concept of surface potential, the proposed method continuously captures the performance degradation across subthreshold and strong inversion regions. Models are comprehensively verified with an industrial 65nm technology. We benchmark the prediction of circuit performance degradation with measured ring oscillator data and simulations of an amplifier.",

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AB - The de facto modeling method to analyze channel-hot-carrier (CHC) is based on substrate current (Isub), which becomes increasingly problematic with technology scaling as various leakage components dominate Isub. In this work, we present a unified approach that directly predicts the change of key transistor parameters under various process and design conditions, for both negative-bias-temperature-instability (NBTI) and CHC degradation. Using the general reaction-diffusion model and the concept of surface potential, the proposed method continuously captures the performance degradation across subthreshold and strong inversion regions. Models are comprehensively verified with an industrial 65nm technology. We benchmark the prediction of circuit performance degradation with measured ring oscillator data and simulations of an amplifier.

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An Integrated Modeling Paradigm of Circuit Reliability for 65nm CMOS Technology

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