An ILP formulation for system level throughput and power optimization in multiprocessor SoC architectures

Krishnan Srinivasan, Karam S. Chatha

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

System-level low power scheduling techniques are required for optimizing the performance and power of embedded applications that are mapped to multiprocessor System-on-Chip (SoC) architectures. In this paper, we present an integer linear programming (ILP) formulation that combines loop transformations (pipelining and unrolling) and system-level low power optimization techniques (dynamic voltage scaling (DVS) and power management (DPM)) to minimize the power consumption, while satisfying the period and deadline constraints of the application. We also present three modifications that relax one or more constraints in the optimal formulation in order to obtain smaller run times. We present experimental analysis by applying the formulations on an MPEG decoder algorithm. All results are compared against two existing techniques. Our formulations result in large system-level power reductions (max: 48.2%, min: 15.92 %, avg: 31.9 %). The modified ILP formulations result in exponential decrease in runtimes, and a corresponding linear degradation in the result quality.

Original languageEnglish (US)
Title of host publicationProceedings of the IEEE International Conference on VLSI Design
Pages255-260
Number of pages6
Volume17
StatePublished - 2004
EventProceedings - 17th International Conference on VLSI Design, Concurrently with the 3rd International Conference on Embedded Systems Design - Mumbai, India
Duration: Jan 5 2004Jan 9 2004

Other

OtherProceedings - 17th International Conference on VLSI Design, Concurrently with the 3rd International Conference on Embedded Systems Design
CountryIndia
CityMumbai
Period1/5/041/9/04

Fingerprint

Linear programming
Throughput
Electric power utilization
Scheduling
Degradation
System-on-chip
Power management
Voltage scaling

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Srinivasan, K., & Chatha, K. S. (2004). An ILP formulation for system level throughput and power optimization in multiprocessor SoC architectures. In Proceedings of the IEEE International Conference on VLSI Design (Vol. 17, pp. 255-260)

An ILP formulation for system level throughput and power optimization in multiprocessor SoC architectures. / Srinivasan, Krishnan; Chatha, Karam S.

Proceedings of the IEEE International Conference on VLSI Design. Vol. 17 2004. p. 255-260.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Srinivasan, K & Chatha, KS 2004, An ILP formulation for system level throughput and power optimization in multiprocessor SoC architectures. in Proceedings of the IEEE International Conference on VLSI Design. vol. 17, pp. 255-260, Proceedings - 17th International Conference on VLSI Design, Concurrently with the 3rd International Conference on Embedded Systems Design, Mumbai, India, 1/5/04.
Srinivasan K, Chatha KS. An ILP formulation for system level throughput and power optimization in multiprocessor SoC architectures. In Proceedings of the IEEE International Conference on VLSI Design. Vol. 17. 2004. p. 255-260
Srinivasan, Krishnan ; Chatha, Karam S. / An ILP formulation for system level throughput and power optimization in multiprocessor SoC architectures. Proceedings of the IEEE International Conference on VLSI Design. Vol. 17 2004. pp. 255-260
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