An ILP formulation for system-level application mapping on network processor architectures

Chris Ostler, Karam S. Chatha

Research output: Chapter in Book/Report/Conference proceedingConference contribution

26 Scopus citations

Abstract

Current day network processors incorporate several architectural features including symmetric multi-processing (SMP), block multi-threading, and multiple memory elements to support the high performance requirements of networking applications. We present an automated system-level design technique for application development on such architectures. The technique incorporates process transformations and block multi-threading aware data mapping to maximize the worst case throughput of the application. We propose integer linear programming formulations for process allocation and data mapping on SMP and block multi-threading based network processors. The paper presents experimental results that evaluate the technique by implementing representative network processing applications on the Intel LXP 2400 architecture. The results demonstrate that our technique is able to generate high-quality mappings of realistic applications on the target architecture within a short time.

Original languageEnglish (US)
Title of host publicationProceedings -Design, Automation and Test in Europe, DATE
Pages99-104
Number of pages6
DOIs
Publication statusPublished - 2007
Event2007 Design, Automation and Test in Europe Conference and Exhibition - Nice Acropolis, France
Duration: Apr 16 2007Apr 20 2007

Other

Other2007 Design, Automation and Test in Europe Conference and Exhibition
CountryFrance
CityNice Acropolis
Period4/16/074/20/07

    Fingerprint

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Ostler, C., & Chatha, K. S. (2007). An ILP formulation for system-level application mapping on network processor architectures. In Proceedings -Design, Automation and Test in Europe, DATE (pp. 99-104). [4211779] https://doi.org/10.1109/DATE.2007.364574