TY - GEN
T1 - An ILP formulation for system-level application mapping on network processor architectures
AU - Ostler, Chris
AU - Chatha, Karam S.
PY - 2007
Y1 - 2007
N2 - Current day network processors incorporate several architectural features including symmetric multi-processing (SMP), block multi-threading, and multiple memory elements to support the high performance requirements of networking applications. We present an automated system-level design technique for application development on such architectures. The technique incorporates process transformations and block multi-threading aware data mapping to maximize the worst case throughput of the application. We propose integer linear programming formulations for process allocation and data mapping on SMP and block multi-threading based network processors. The paper presents experimental results that evaluate the technique by implementing representative network processing applications on the Intel LXP 2400 architecture. The results demonstrate that our technique is able to generate high-quality mappings of realistic applications on the target architecture within a short time.
AB - Current day network processors incorporate several architectural features including symmetric multi-processing (SMP), block multi-threading, and multiple memory elements to support the high performance requirements of networking applications. We present an automated system-level design technique for application development on such architectures. The technique incorporates process transformations and block multi-threading aware data mapping to maximize the worst case throughput of the application. We propose integer linear programming formulations for process allocation and data mapping on SMP and block multi-threading based network processors. The paper presents experimental results that evaluate the technique by implementing representative network processing applications on the Intel LXP 2400 architecture. The results demonstrate that our technique is able to generate high-quality mappings of realistic applications on the target architecture within a short time.
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U2 - 10.1109/DATE.2007.364574
DO - 10.1109/DATE.2007.364574
M3 - Conference contribution
AN - SCOPUS:34548301614
SN - 3981080122
SN - 9783981080124
T3 - Proceedings -Design, Automation and Test in Europe, DATE
SP - 99
EP - 104
BT - Proceedings - 2007 Design, Automation and Test in Europe Conference and Exhibition, DATE 2007
T2 - 2007 Design, Automation and Test in Europe Conference and Exhibition
Y2 - 16 April 2007 through 20 April 2007
ER -