An H.264/SVC memory architecture supporting spatial and course-grained quality scalabilities

Niranjan D. Narvekar; Bharatan Konnanath; Shalin Mehta; Santosh Chintalapati; Ismail AlKamal; Chaitali Chakrabarti; Lina Karam

doi:10.1109/ICIP.2009.5414130

An H.264/SVC memory architecture supporting spatial and course-grained quality scalabilities

Niranjan D. Narvekar, Bharatan Konnanath, Shalin Mehta, Santosh Chintalapati, Ismail AlKamal, Chaitali Chakrabarti, Lina Karam

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Scopus citations

Abstract

The standardized Scalable Video Coding (SVC) extension of H.264/AVC achieves significant improvements in coding efficiency relative to the scalable profiles of prior video coding standards, but its computational complexity and memory access requirements make the design of a low power hardware architecture a challenging task. This paper presents an SVC decoder architecture supporting spatial and coarse-grained quality scalability. The architecture optimizes the size of the on-chip memory and reduces the powerconsuming and time-intensive external memory accesses.

Original language	English (US)
Title of host publication	2009 IEEE International Conference on Image Processing, ICIP 2009 - Proceedings
Publisher	IEEE Computer Society
Pages	2661-2664
Number of pages	4
ISBN (Print)	9781424456543
DOIs	https://doi.org/10.1109/ICIP.2009.5414130
State	Published - Jan 1 2009
Event	2009 IEEE International Conference on Image Processing, ICIP 2009 - Cairo, Egypt Duration: Nov 7 2009 → Nov 10 2009

Publication series

Name	Proceedings - International Conference on Image Processing, ICIP
ISSN (Print)	1522-4880

Other

Other	2009 IEEE International Conference on Image Processing, ICIP 2009
Country/Territory	Egypt
City	Cairo
Period	11/7/09 → 11/10/09

Keywords

CGS
Decoder architecture
H.264/AVC
Scalable Video Coding (SVC)

ASJC Scopus subject areas

Software
Computer Vision and Pattern Recognition
Signal Processing

Access to Document

10.1109/ICIP.2009.5414130

Cite this

Narvekar, N. D., Konnanath, B., Mehta, S., Chintalapati, S., AlKamal, I., Chakrabarti, C., & Karam, L. (2009). An H.264/SVC memory architecture supporting spatial and course-grained quality scalabilities. In 2009 IEEE International Conference on Image Processing, ICIP 2009 - Proceedings (pp. 2661-2664). [5414130] (Proceedings - International Conference on Image Processing, ICIP). IEEE Computer Society. https://doi.org/10.1109/ICIP.2009.5414130

An H.264/SVC memory architecture supporting spatial and course-grained quality scalabilities. / Narvekar, Niranjan D.; Konnanath, Bharatan; Mehta, Shalin et al.
2009 IEEE International Conference on Image Processing, ICIP 2009 - Proceedings. IEEE Computer Society, 2009. p. 2661-2664 5414130 (Proceedings - International Conference on Image Processing, ICIP).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Narvekar, ND, Konnanath, B, Mehta, S, Chintalapati, S, AlKamal, I, Chakrabarti, C & Karam, L 2009, An H.264/SVC memory architecture supporting spatial and course-grained quality scalabilities. in 2009 IEEE International Conference on Image Processing, ICIP 2009 - Proceedings., 5414130, Proceedings - International Conference on Image Processing, ICIP, IEEE Computer Society, pp. 2661-2664, 2009 IEEE International Conference on Image Processing, ICIP 2009, Cairo, Egypt, 11/7/09. https://doi.org/10.1109/ICIP.2009.5414130

Narvekar ND, Konnanath B, Mehta S, Chintalapati S, AlKamal I, Chakrabarti C et al. An H.264/SVC memory architecture supporting spatial and course-grained quality scalabilities. In 2009 IEEE International Conference on Image Processing, ICIP 2009 - Proceedings. IEEE Computer Society. 2009. p. 2661-2664. 5414130. (Proceedings - International Conference on Image Processing, ICIP). doi: 10.1109/ICIP.2009.5414130

@inproceedings{c2c5c403ec8345308a2528b92481aee9,

title = "An H.264/SVC memory architecture supporting spatial and course-grained quality scalabilities",

abstract = "The standardized Scalable Video Coding (SVC) extension of H.264/AVC achieves significant improvements in coding efficiency relative to the scalable profiles of prior video coding standards, but its computational complexity and memory access requirements make the design of a low power hardware architecture a challenging task. This paper presents an SVC decoder architecture supporting spatial and coarse-grained quality scalability. The architecture optimizes the size of the on-chip memory and reduces the powerconsuming and time-intensive external memory accesses.",

keywords = "CGS, Decoder architecture, H.264/AVC, Scalable Video Coding (SVC)",

author = "Narvekar, {Niranjan D.} and Bharatan Konnanath and Shalin Mehta and Santosh Chintalapati and Ismail AlKamal and Chaitali Chakrabarti and Lina Karam",

year = "2009",

month = jan,

day = "1",

doi = "10.1109/ICIP.2009.5414130",

language = "English (US)",

isbn = "9781424456543",

series = "Proceedings - International Conference on Image Processing, ICIP",

publisher = "IEEE Computer Society",

pages = "2661--2664",

booktitle = "2009 IEEE International Conference on Image Processing, ICIP 2009 - Proceedings",

note = "2009 IEEE International Conference on Image Processing, ICIP 2009 ; Conference date: 07-11-2009 Through 10-11-2009",

}

TY - GEN

T1 - An H.264/SVC memory architecture supporting spatial and course-grained quality scalabilities

AU - Narvekar, Niranjan D.

AU - Konnanath, Bharatan

AU - Mehta, Shalin

AU - Chintalapati, Santosh

AU - AlKamal, Ismail

AU - Chakrabarti, Chaitali

AU - Karam, Lina

PY - 2009/1/1

Y1 - 2009/1/1

N2 - The standardized Scalable Video Coding (SVC) extension of H.264/AVC achieves significant improvements in coding efficiency relative to the scalable profiles of prior video coding standards, but its computational complexity and memory access requirements make the design of a low power hardware architecture a challenging task. This paper presents an SVC decoder architecture supporting spatial and coarse-grained quality scalability. The architecture optimizes the size of the on-chip memory and reduces the powerconsuming and time-intensive external memory accesses.

AB - The standardized Scalable Video Coding (SVC) extension of H.264/AVC achieves significant improvements in coding efficiency relative to the scalable profiles of prior video coding standards, but its computational complexity and memory access requirements make the design of a low power hardware architecture a challenging task. This paper presents an SVC decoder architecture supporting spatial and coarse-grained quality scalability. The architecture optimizes the size of the on-chip memory and reduces the powerconsuming and time-intensive external memory accesses.

KW - CGS

KW - Decoder architecture

KW - H.264/AVC

KW - Scalable Video Coding (SVC)

UR - http://www.scopus.com/inward/record.url?scp=77951953817&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=77951953817&partnerID=8YFLogxK

U2 - 10.1109/ICIP.2009.5414130

DO - 10.1109/ICIP.2009.5414130

M3 - Conference contribution

AN - SCOPUS:77951953817

SN - 9781424456543

T3 - Proceedings - International Conference on Image Processing, ICIP

SP - 2661

EP - 2664

BT - 2009 IEEE International Conference on Image Processing, ICIP 2009 - Proceedings

PB - IEEE Computer Society

T2 - 2009 IEEE International Conference on Image Processing, ICIP 2009

Y2 - 7 November 2009 through 10 November 2009

ER -

An H.264/SVC memory architecture supporting spatial and course-grained quality scalabilities

Abstract

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Keywords

ASJC Scopus subject areas

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