An H.264/SVC memory architecture supporting spatial and course-grained quality scalabilities

Niranjan D. Narvekar, Bharatan Konnanath, Shalin Mehta, Santosh Chintalapati, Ismail AlKamal, Chaitali Chakrabarti, Lina Karam

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

The standardized Scalable Video Coding (SVC) extension of H.264/AVC achieves significant improvements in coding efficiency relative to the scalable profiles of prior video coding standards, but its computational complexity and memory access requirements make the design of a low power hardware architecture a challenging task. This paper presents an SVC decoder architecture supporting spatial and coarse-grained quality scalability. The architecture optimizes the size of the on-chip memory and reduces the powerconsuming and time-intensive external memory accesses.

Original languageEnglish (US)
Title of host publicationProceedings - International Conference on Image Processing, ICIP
PublisherIEEE Computer Society
Pages2661-2664
Number of pages4
ISBN (Print)9781424456543
DOIs
StatePublished - 2009
Event2009 IEEE International Conference on Image Processing, ICIP 2009 - Cairo, Egypt
Duration: Nov 7 2009Nov 10 2009

Other

Other2009 IEEE International Conference on Image Processing, ICIP 2009
CountryEgypt
CityCairo
Period11/7/0911/10/09

Fingerprint

Scalable video coding
Memory architecture
Scalability
Data storage equipment
Image coding
Computational complexity
Hardware

Keywords

  • CGS
  • Decoder architecture
  • H.264/AVC
  • Scalable Video Coding (SVC)

ASJC Scopus subject areas

  • Software
  • Computer Vision and Pattern Recognition
  • Signal Processing

Cite this

Narvekar, N. D., Konnanath, B., Mehta, S., Chintalapati, S., AlKamal, I., Chakrabarti, C., & Karam, L. (2009). An H.264/SVC memory architecture supporting spatial and course-grained quality scalabilities. In Proceedings - International Conference on Image Processing, ICIP (pp. 2661-2664). [5414130] IEEE Computer Society. https://doi.org/10.1109/ICIP.2009.5414130

An H.264/SVC memory architecture supporting spatial and course-grained quality scalabilities. / Narvekar, Niranjan D.; Konnanath, Bharatan; Mehta, Shalin; Chintalapati, Santosh; AlKamal, Ismail; Chakrabarti, Chaitali; Karam, Lina.

Proceedings - International Conference on Image Processing, ICIP. IEEE Computer Society, 2009. p. 2661-2664 5414130.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Narvekar, ND, Konnanath, B, Mehta, S, Chintalapati, S, AlKamal, I, Chakrabarti, C & Karam, L 2009, An H.264/SVC memory architecture supporting spatial and course-grained quality scalabilities. in Proceedings - International Conference on Image Processing, ICIP., 5414130, IEEE Computer Society, pp. 2661-2664, 2009 IEEE International Conference on Image Processing, ICIP 2009, Cairo, Egypt, 11/7/09. https://doi.org/10.1109/ICIP.2009.5414130
Narvekar ND, Konnanath B, Mehta S, Chintalapati S, AlKamal I, Chakrabarti C et al. An H.264/SVC memory architecture supporting spatial and course-grained quality scalabilities. In Proceedings - International Conference on Image Processing, ICIP. IEEE Computer Society. 2009. p. 2661-2664. 5414130 https://doi.org/10.1109/ICIP.2009.5414130
Narvekar, Niranjan D. ; Konnanath, Bharatan ; Mehta, Shalin ; Chintalapati, Santosh ; AlKamal, Ismail ; Chakrabarti, Chaitali ; Karam, Lina. / An H.264/SVC memory architecture supporting spatial and course-grained quality scalabilities. Proceedings - International Conference on Image Processing, ICIP. IEEE Computer Society, 2009. pp. 2661-2664
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