An energy efficient SAR ADC with lowest total switching energy consumption

B. Ghanavati, E. Abiri, A. Keyhani, M. R. Salehi, A. Sanyal

Research output: Contribution to journalArticlepeer-review

4 Scopus citations

Abstract

A new capacitor switching scheme with considerable energy saving for successive approximation register (SAR) analog to digital converter (ADC) is presented. Employing different switching sequence and also one switching event in a cycle in this technique, result in 97.67% reduction in switching energy. Besides that, in the proposed method, an 8 × reduction in total capacitance compared to the conventional architectures achieved by benefiting from LSB split capacitor array. Furthermore, the proposed technique shows the minimum power dissipation in driving the switches since it has only one switching event per cycle and lowest capacitor array compared to the other techniques. Employed the proposed switching scheme, a 10-bit 1-kS/s SAR ADC is designed in 0.18-µm CMOS technology with an active area of 0.025 mm2. With a 1-V power supply for analog and 0.5-V for digital circuit, the ADC achieves an ENOB of 9.73 bits and a FoM of 4.1 fJ/conversion-step. The proposed ADC can find application in biomedical engineering systems and other fields which low power consumption is needed.

Original languageEnglish (US)
Pages (from-to)123-133
Number of pages11
JournalAnalog Integrated Circuits and Signal Processing
Volume97
Issue number1
DOIs
StatePublished - Oct 1 2018
Externally publishedYes

Keywords

  • Analog-to-digital converter
  • Digital-to-analog converter (DAC)
  • LSB split capacitive technique
  • Successive approximation analog-to-digital converter (SAR ADC)
  • Switching energy
  • Ultra-low power

ASJC Scopus subject areas

  • Signal Processing
  • Hardware and Architecture
  • Surfaces, Coatings and Films

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