An Energy Efficient, Robust Differential Mode D-Flip-Flop (KVFF)

Sarma Vrudhula (Inventor)

Research output: Patent

Abstract

The basic building block that makes computer memory and sequential logic circuits possible is the flip flop. Flip flops are a circuit with two interconnected logic gates and two stable output states. D- Flip flops, or delay flip flops, are used to create a delay in the progress of data through a circuit to prevent indeterminate outputs, where the signal from both outputs is the same. There are two types of D-flip flops currently at the top of the market. The first is known as the Master-Slave style (MSFF). MSFF are very widely used in conventional circuit design, but are very slow in terms of overall delay. The second type is the Strong-Arm flip flop (SAFF), which is inherently faster and more energy-efficient than MSFF. Unfortunately, SAFF are prone to functional failures, so they are unable to replace MSFF. Researchers at Arizona State University have invented a new type of D-flip flop, called KVFF. KVFF combines the energy efficiency and speed of SAFF with the robustness of MSFF. Therefore, KVFF are a safer replacement for MSFF yielding faster and/or low power circuits with the same robustness. Potential Applications ASIC circuits Process Controls Computing Circuit Design Semiconductors Electronics Benefits and Advantages Speed KVFF is 30% faster than standard master-slave process control methods, resulting in faster low power circuits. Energy efficiency KVFF is 30% more energy efficient than standard master-slave process control methods. Accuracy Very robust against noise and process variation, with an improved delay spread over standard master-slave flip-flop process control technologies. Download Original PDF For more information about the inventor(s) and their research, please see Dr. Sarma Vrudhula's directory webpage
Original languageEnglish (US)
Publication statusPublished - Mar 24 2015

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