An embedded microprocessor radiation hardened by microarchitecture and circuits

Lawrence T. Clark, Dan W. Patterson, Chandarasekaran Ramamurthy, Keith Holbert

Research output: Contribution to journalArticle

10 Scopus citations

Abstract

A radiation hardened by design embedded microprocessor is presented. The design uses multiple approaches to minimize the performance reduction from hardening, while simultaneously limiting the power increase. The speculative portions of the pipeline are protected by microarchitecture approaches, i.e., the speculative pipeline is dual redundant, whereby instructions that have errors in one copy cause a pipeline restart - only matching results commit to architectural state. The register file is dual redundant with mechanisms for correction using one copy whose parity is correct. The data cache memory is write-through, allowing protection with parity. The remaining architectural state is protected via hardened circuits. These are implemented with self-correcting triple mode redundant (TMR) flip-flops and TMR logic. The design, implemented here on a 90-nm bulk CMOS process, achieves unprecedented single event effects hardness and 400+ MHz operating frequency at less than 500 mW power consumption. The main constituent circuit hardening approaches have been fabricated and tested separately. Broad beam testing of the constituent circuits has resulted in no uncorrectable soft errors below 100 MeV-cm2\mg LETEFF. We describe the CAD flows used to ensure node separation to achieve high immunity to multiple node charge collection and discuss the relative costs of the chosen hardening techniques.

Original languageEnglish (US)
Article number7079491
Pages (from-to)382-395
Number of pages14
JournalIEEE Transactions on Computers
Volume65
Issue number2
DOIs
StatePublished - Feb 1 2016

Keywords

  • cache memory
  • microprocessor
  • Radiation hardening by design (RHBD)
  • single event transients
  • single-event effects
  • soft error mitigation
  • total ionizing dose

ASJC Scopus subject areas

  • Hardware and Architecture
  • Software
  • Computational Theory and Mathematics
  • Theoretical Computer Science

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