An embedded architecture for energy-efficient stream computing

Stream processing has emerged as an important model of computation in the context of multimedia and communication subsystems of embedded system-on-chip (SoC) architectures. The dataflow nature of streaming applications allows them to be most naturally expressed as a set of kernels iteratively operating on continuous streams of data. The kernels are computationally intensive and are characterized by high throughput requirements. We present StreamEngine, an embedded architecture for energy-efficient computation of stream kernels. StreamEngine introduces an instruction locking mechanism that exploits the iterative nature of streams and enables fine-grain instruction reuse. We also adopt a context-aware dataflow execution (CDE) model to exploit instruction-level parallelism (ILP) and data-level parallelism (DLP) within the stream kernels. We evaluate the performance and energy-efficiency of our architecture for stream kernel benchmarks by implementing the architecture with TSMC 45 nm process, and comparison with an embedded RISC processor.