Abstract

Nonvolatile memory cells based on solid electrolytes have many desirable attributes, including low-voltage and low-current operation and a simple process that allows them to be integrated with conventional CMOS processes with minimal additional masking layers. In this paper, we present a 2-kb memory block/testbed (1024 elements) using solid electrolyte cells. The compact memory design addresses many of the unusual operational issues associated with the solid electrolyte elements and allows for two digital bits to be stored and read from each cell with minimal circuitry. The design was fabricated in 0.18-μm CMOS technology and the simulation and physical data are presented. Multilevel-cell (MLC) operation was demonstrated for a 10-μA reference current with a 437-ns cycle time and sub-40-ns access times.

Original languageEnglish (US)
Pages (from-to)1383-1391
Number of pages9
JournalIEEE Journal of Solid-State Circuits
Volume42
Issue number6
DOIs
StatePublished - Jun 1 2007

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Keywords

  • Multilevel cell (MLC)
  • Nonvolatile memory
  • Programmable metallization cell
  • Solid electrolyte

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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