An efficient timestamp-based monitoring approach to test timing constraints of cyber-physical systems

Mohammadreza Mehrabian, Mohammad Khayatian, Ahmed Mousa, Aviral Shrivastava, Ya Shian Li-Baboud, Patricia Derler, Edward Griffor, Hugo A. Andrade, Marc Wiess, John C. Eidson, Dhananjay Anand

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

Formal specifications on temporal behavior of Cyber-Physical Systems (CPS) is essential for verification of performance and safety. Existing solutions for verifying the satisfaction of temporal constraints on a CPS are compute and resource intensive since they require buffering signals from the CPS prior to constraint checking. We present an online approach, based on Timestamp Temporal Logic (TTL), for monitoring the timing constraints in CPS. The approach reduces the computation and memory requirements by processing the timestamps of pertinent events reducing the need to capture the full data set from the signal sampling. The signal buffer size bears a geometric relationship to the dimension of the signal vector, the time interval being considered, and the sampling resolution. Since monitoring logic is typically implemented on Field Programmable Gate Arrays (FPGAs) for efficient monitoring of multiple signals simultaneously, the space required to store the buffered data becomes the limiting resource. The monitoring logic, for the timing constraints on the Flying Paster (a printing application requiring synchronization between two motors), is illustrated in this paper to demonstrate a geometric reduction in memory and computational resources in the realization of an online monitor.

Original languageEnglish (US)
Title of host publicationProceedings of the 55th Annual Design Automation Conference, DAC 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
VolumePart F137710
ISBN (Print)9781450357005
DOIs
StatePublished - Jun 24 2018
Event55th Annual Design Automation Conference, DAC 2018 - San Francisco, United States
Duration: Jun 24 2018Jun 29 2018

Other

Other55th Annual Design Automation Conference, DAC 2018
CountryUnited States
CitySan Francisco
Period6/24/186/29/18

Fingerprint

Timestamp
Timing
Monitoring
Resources
Signal sampling
Data storage equipment
Temporal logic
Logic
Temporal Constraints
Formal Specification
Field programmable gate arrays (FPGA)
Printing
Temporal Logic
Synchronization
Field Programmable Gate Array
Buffer
Sampling
Monitor
Limiting
Safety

ASJC Scopus subject areas

  • Computer Science Applications
  • Control and Systems Engineering
  • Electrical and Electronic Engineering
  • Modeling and Simulation

Cite this

Mehrabian, M., Khayatian, M., Mousa, A., Shrivastava, A., Li-Baboud, Y. S., Derler, P., ... Anand, D. (2018). An efficient timestamp-based monitoring approach to test timing constraints of cyber-physical systems. In Proceedings of the 55th Annual Design Automation Conference, DAC 2018 (Vol. Part F137710). [a144] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1145/3195970.3196130

An efficient timestamp-based monitoring approach to test timing constraints of cyber-physical systems. / Mehrabian, Mohammadreza; Khayatian, Mohammad; Mousa, Ahmed; Shrivastava, Aviral; Li-Baboud, Ya Shian; Derler, Patricia; Griffor, Edward; Andrade, Hugo A.; Wiess, Marc; Eidson, John C.; Anand, Dhananjay.

Proceedings of the 55th Annual Design Automation Conference, DAC 2018. Vol. Part F137710 Institute of Electrical and Electronics Engineers Inc., 2018. a144.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Mehrabian, M, Khayatian, M, Mousa, A, Shrivastava, A, Li-Baboud, YS, Derler, P, Griffor, E, Andrade, HA, Wiess, M, Eidson, JC & Anand, D 2018, An efficient timestamp-based monitoring approach to test timing constraints of cyber-physical systems. in Proceedings of the 55th Annual Design Automation Conference, DAC 2018. vol. Part F137710, a144, Institute of Electrical and Electronics Engineers Inc., 55th Annual Design Automation Conference, DAC 2018, San Francisco, United States, 6/24/18. https://doi.org/10.1145/3195970.3196130
Mehrabian M, Khayatian M, Mousa A, Shrivastava A, Li-Baboud YS, Derler P et al. An efficient timestamp-based monitoring approach to test timing constraints of cyber-physical systems. In Proceedings of the 55th Annual Design Automation Conference, DAC 2018. Vol. Part F137710. Institute of Electrical and Electronics Engineers Inc. 2018. a144 https://doi.org/10.1145/3195970.3196130
Mehrabian, Mohammadreza ; Khayatian, Mohammad ; Mousa, Ahmed ; Shrivastava, Aviral ; Li-Baboud, Ya Shian ; Derler, Patricia ; Griffor, Edward ; Andrade, Hugo A. ; Wiess, Marc ; Eidson, John C. ; Anand, Dhananjay. / An efficient timestamp-based monitoring approach to test timing constraints of cyber-physical systems. Proceedings of the 55th Annual Design Automation Conference, DAC 2018. Vol. Part F137710 Institute of Electrical and Electronics Engineers Inc., 2018.
@inproceedings{73c513612bee487b8218f591a63916ae,
title = "An efficient timestamp-based monitoring approach to test timing constraints of cyber-physical systems",
abstract = "Formal specifications on temporal behavior of Cyber-Physical Systems (CPS) is essential for verification of performance and safety. Existing solutions for verifying the satisfaction of temporal constraints on a CPS are compute and resource intensive since they require buffering signals from the CPS prior to constraint checking. We present an online approach, based on Timestamp Temporal Logic (TTL), for monitoring the timing constraints in CPS. The approach reduces the computation and memory requirements by processing the timestamps of pertinent events reducing the need to capture the full data set from the signal sampling. The signal buffer size bears a geometric relationship to the dimension of the signal vector, the time interval being considered, and the sampling resolution. Since monitoring logic is typically implemented on Field Programmable Gate Arrays (FPGAs) for efficient monitoring of multiple signals simultaneously, the space required to store the buffered data becomes the limiting resource. The monitoring logic, for the timing constraints on the Flying Paster (a printing application requiring synchronization between two motors), is illustrated in this paper to demonstrate a geometric reduction in memory and computational resources in the realization of an online monitor.",
author = "Mohammadreza Mehrabian and Mohammad Khayatian and Ahmed Mousa and Aviral Shrivastava and Li-Baboud, {Ya Shian} and Patricia Derler and Edward Griffor and Andrade, {Hugo A.} and Marc Wiess and Eidson, {John C.} and Dhananjay Anand",
year = "2018",
month = "6",
day = "24",
doi = "10.1145/3195970.3196130",
language = "English (US)",
isbn = "9781450357005",
volume = "Part F137710",
booktitle = "Proceedings of the 55th Annual Design Automation Conference, DAC 2018",
publisher = "Institute of Electrical and Electronics Engineers Inc.",

}

TY - GEN

T1 - An efficient timestamp-based monitoring approach to test timing constraints of cyber-physical systems

AU - Mehrabian, Mohammadreza

AU - Khayatian, Mohammad

AU - Mousa, Ahmed

AU - Shrivastava, Aviral

AU - Li-Baboud, Ya Shian

AU - Derler, Patricia

AU - Griffor, Edward

AU - Andrade, Hugo A.

AU - Wiess, Marc

AU - Eidson, John C.

AU - Anand, Dhananjay

PY - 2018/6/24

Y1 - 2018/6/24

N2 - Formal specifications on temporal behavior of Cyber-Physical Systems (CPS) is essential for verification of performance and safety. Existing solutions for verifying the satisfaction of temporal constraints on a CPS are compute and resource intensive since they require buffering signals from the CPS prior to constraint checking. We present an online approach, based on Timestamp Temporal Logic (TTL), for monitoring the timing constraints in CPS. The approach reduces the computation and memory requirements by processing the timestamps of pertinent events reducing the need to capture the full data set from the signal sampling. The signal buffer size bears a geometric relationship to the dimension of the signal vector, the time interval being considered, and the sampling resolution. Since monitoring logic is typically implemented on Field Programmable Gate Arrays (FPGAs) for efficient monitoring of multiple signals simultaneously, the space required to store the buffered data becomes the limiting resource. The monitoring logic, for the timing constraints on the Flying Paster (a printing application requiring synchronization between two motors), is illustrated in this paper to demonstrate a geometric reduction in memory and computational resources in the realization of an online monitor.

AB - Formal specifications on temporal behavior of Cyber-Physical Systems (CPS) is essential for verification of performance and safety. Existing solutions for verifying the satisfaction of temporal constraints on a CPS are compute and resource intensive since they require buffering signals from the CPS prior to constraint checking. We present an online approach, based on Timestamp Temporal Logic (TTL), for monitoring the timing constraints in CPS. The approach reduces the computation and memory requirements by processing the timestamps of pertinent events reducing the need to capture the full data set from the signal sampling. The signal buffer size bears a geometric relationship to the dimension of the signal vector, the time interval being considered, and the sampling resolution. Since monitoring logic is typically implemented on Field Programmable Gate Arrays (FPGAs) for efficient monitoring of multiple signals simultaneously, the space required to store the buffered data becomes the limiting resource. The monitoring logic, for the timing constraints on the Flying Paster (a printing application requiring synchronization between two motors), is illustrated in this paper to demonstrate a geometric reduction in memory and computational resources in the realization of an online monitor.

UR - http://www.scopus.com/inward/record.url?scp=85053684877&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85053684877&partnerID=8YFLogxK

U2 - 10.1145/3195970.3196130

DO - 10.1145/3195970.3196130

M3 - Conference contribution

SN - 9781450357005

VL - Part F137710

BT - Proceedings of the 55th Annual Design Automation Conference, DAC 2018

PB - Institute of Electrical and Electronics Engineers Inc.

ER -