An efficient switch design for scheduling real-time multicast traffic

Deming Liu, Yann-Hang Lee

Research output: Contribution to journalArticle

Abstract

Abstract. In this paper we put forth a switch design in terms of architecture and service discipline for real-time multicast traffic in packet switching networks. A parallel switching architecture called POQ (parallel output-queued) is employed, which take the advantages of both OQ (output-queued) and IQ (inputqueued) switch architectures, i.e., non-blocking and low speedup of switch buffer. Basing on the POQ architecture we propose a hierarchical service discipline called H-EDF-RR (hierarchical earliest-deadline-first round-robin), which intends to simultaneously schedule both unicast and multicast traffic composed of fixed-length cells with guaranteed performances. Analyses show that this design can provide tight delay bounds and buffer requirements, and has computational complexity of O(l). These properties make the proposed switch design well suitable in real-time distributed systems.

Original languageEnglish (US)
Pages (from-to)194-207
Number of pages14
JournalLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume2968
StatePublished - 2004

Fingerprint

Multicast
Switch
Buffers
Scheduling
Switches
Traffic
Real-time
Computer Communication Networks
Songbirds
Computer Systems
Buffer
Output
Appointments and Schedules
Earliest Deadline First
Packet Switching
Packet switching
Parallel architectures
Packet networks
Parallel Architectures
Switching networks

Keywords

  • Earliest deadline first round robin
  • Multicasting
  • Packet switching network
  • Quality of service
  • Real-time communications

ASJC Scopus subject areas

  • Computer Science(all)
  • Biochemistry, Genetics and Molecular Biology(all)
  • Theoretical Computer Science

Cite this

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AB - Abstract. In this paper we put forth a switch design in terms of architecture and service discipline for real-time multicast traffic in packet switching networks. A parallel switching architecture called POQ (parallel output-queued) is employed, which take the advantages of both OQ (output-queued) and IQ (inputqueued) switch architectures, i.e., non-blocking and low speedup of switch buffer. Basing on the POQ architecture we propose a hierarchical service discipline called H-EDF-RR (hierarchical earliest-deadline-first round-robin), which intends to simultaneously schedule both unicast and multicast traffic composed of fixed-length cells with guaranteed performances. Analyses show that this design can provide tight delay bounds and buffer requirements, and has computational complexity of O(l). These properties make the proposed switch design well suitable in real-time distributed systems.

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