An efficient method to identify critical gates under circuit aging

Wenping Wang, Zile Wei, Shengqi Yang, Yu Cao

Research output: Chapter in Book/Report/Conference proceedingConference contribution

144 Citations (Scopus)

Abstract

Negative Bias Temperature Instability (NBTI) is the leading factor of circuit performance degradation. Due to its complex dependence on operating conditions, especially signal probability, it is a tremendous challenge to accurately predict the degradation rate in reality. On the other hand, we demonstrate in this work that it is feasible to reliably predict the relative importance of gates under NBTI. By identifying critical gates that are the most important ones for timing degradation, we will be able to effectively protect the circuit from aging, with the minimum design overhead. The proposed method is based on a new timing analysis framework that integrates a NBTI-aware library. For each potential critical path, we prove that there exists a particular signal probability, which leads to the worst case of timing degradation. The search of such worst case signal probability provides a safe guardband for the degradation, yet avoiding overly pessimistic analysis. By applying this method to ISCAS and ITC benchmark circuits at the 65nm node, we demonstrate that in average only 1% of total gates need to be protected in order to control the timing degradation within 10% in ten years. Since this method only requires one-time analysis of each critical path, it is very efficient in computation. With the information of critical gates available, it further enables other resilient design techniques to mitigate circuit aging under NBTI.

Original languageEnglish (US)
Title of host publicationIEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
Pages735-740
Number of pages6
DOIs
StatePublished - 2007
Event2007 IEEE/ACM International Conference on Computer-Aided Design, ICCAD - San Jose, CA, United States
Duration: Nov 4 2007Nov 8 2007

Other

Other2007 IEEE/ACM International Conference on Computer-Aided Design, ICCAD
CountryUnited States
CitySan Jose, CA
Period11/4/0711/8/07

Fingerprint

Aging of materials
Degradation
Networks (circuits)
Negative bias temperature instability

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Wang, W., Wei, Z., Yang, S., & Cao, Y. (2007). An efficient method to identify critical gates under circuit aging. In IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD (pp. 735-740). [4397353] https://doi.org/10.1109/ICCAD.2007.4397353

An efficient method to identify critical gates under circuit aging. / Wang, Wenping; Wei, Zile; Yang, Shengqi; Cao, Yu.

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD. 2007. p. 735-740 4397353.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Wang, W, Wei, Z, Yang, S & Cao, Y 2007, An efficient method to identify critical gates under circuit aging. in IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD., 4397353, pp. 735-740, 2007 IEEE/ACM International Conference on Computer-Aided Design, ICCAD, San Jose, CA, United States, 11/4/07. https://doi.org/10.1109/ICCAD.2007.4397353
Wang W, Wei Z, Yang S, Cao Y. An efficient method to identify critical gates under circuit aging. In IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD. 2007. p. 735-740. 4397353 https://doi.org/10.1109/ICCAD.2007.4397353
Wang, Wenping ; Wei, Zile ; Yang, Shengqi ; Cao, Yu. / An efficient method to identify critical gates under circuit aging. IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD. 2007. pp. 735-740
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