TY - GEN
T1 - An efficient method to identify critical gates under circuit aging
AU - Wang, Wenping
AU - Wei, Zile
AU - Yang, Shengqi
AU - Cao, Yu
PY - 2007
Y1 - 2007
N2 - Negative Bias Temperature Instability (NBTI) is the leading factor of circuit performance degradation. Due to its complex dependence on operating conditions, especially signal probability, it is a tremendous challenge to accurately predict the degradation rate in reality. On the other hand, we demonstrate in this work that it is feasible to reliably predict the relative importance of gates under NBTI. By identifying critical gates that are the most important ones for timing degradation, we will be able to effectively protect the circuit from aging, with the minimum design overhead. The proposed method is based on a new timing analysis framework that integrates a NBTI-aware library. For each potential critical path, we prove that there exists a particular signal probability, which leads to the worst case of timing degradation. The search of such worst case signal probability provides a safe guardband for the degradation, yet avoiding overly pessimistic analysis. By applying this method to ISCAS and ITC benchmark circuits at the 65nm node, we demonstrate that in average only 1% of total gates need to be protected in order to control the timing degradation within 10% in ten years. Since this method only requires one-time analysis of each critical path, it is very efficient in computation. With the information of critical gates available, it further enables other resilient design techniques to mitigate circuit aging under NBTI.
AB - Negative Bias Temperature Instability (NBTI) is the leading factor of circuit performance degradation. Due to its complex dependence on operating conditions, especially signal probability, it is a tremendous challenge to accurately predict the degradation rate in reality. On the other hand, we demonstrate in this work that it is feasible to reliably predict the relative importance of gates under NBTI. By identifying critical gates that are the most important ones for timing degradation, we will be able to effectively protect the circuit from aging, with the minimum design overhead. The proposed method is based on a new timing analysis framework that integrates a NBTI-aware library. For each potential critical path, we prove that there exists a particular signal probability, which leads to the worst case of timing degradation. The search of such worst case signal probability provides a safe guardband for the degradation, yet avoiding overly pessimistic analysis. By applying this method to ISCAS and ITC benchmark circuits at the 65nm node, we demonstrate that in average only 1% of total gates need to be protected in order to control the timing degradation within 10% in ten years. Since this method only requires one-time analysis of each critical path, it is very efficient in computation. With the information of critical gates available, it further enables other resilient design techniques to mitigate circuit aging under NBTI.
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U2 - 10.1109/ICCAD.2007.4397353
DO - 10.1109/ICCAD.2007.4397353
M3 - Conference contribution
AN - SCOPUS:49549122051
SN - 1424413826
SN - 9781424413829
T3 - IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
SP - 735
EP - 740
BT - 2007 IEEE/ACM International Conference on Computer-Aided Design, ICCAD
T2 - 2007 IEEE/ACM International Conference on Computer-Aided Design, ICCAD
Y2 - 4 November 2007 through 8 November 2007
ER -