TY - JOUR
T1 - An Efficient Control Point Insertion Technique for Leakage Reduction of Scaled CMOS Circuits
AU - Rahman, H.
AU - Chakrabarti, Chaitali
N1 - Funding Information:
Manuscript received June 28, 2004; revised November 8, 2004. This work was supported by the National Science Foundation under Grant EEC-9523338, the State of Arizona, and an industrial consortium.This paper was recommended by Associate Editor M. Soma. The authors are with Arizona State University, Tempe, AZ 85287 USA (e-mail: hafij@asu.edu; chaitali@asu.edu). Digital Object Identifier 10.1109/TCSII.2005.849026
PY - 2005/8
Y1 - 2005/8
N2 - Leakage power reduction is extremely important in the design of scaled CMOS logic circuits. The dominant leakage components of such circuits are the subthreshold leakage and the thin-oxide gate leakage. This paper describes an efficient leakage reduction method that considers both these components, and is based on the selective insertion of control points. The selection is based on the leakage reduction potential and the delay insensitivity of the candidate gates. Simulations on the ISCAS85 benchmark circuits show that this method results in ∽67% leakage reduction with no speed degradation when control points are added to 93% of the gates compared to the leakage of the baseline circuit whose inputs have been subjected to the minimum leakage vector.
AB - Leakage power reduction is extremely important in the design of scaled CMOS logic circuits. The dominant leakage components of such circuits are the subthreshold leakage and the thin-oxide gate leakage. This paper describes an efficient leakage reduction method that considers both these components, and is based on the selective insertion of control points. The selection is based on the leakage reduction potential and the delay insensitivity of the candidate gates. Simulations on the ISCAS85 benchmark circuits show that this method results in ∽67% leakage reduction with no speed degradation when control points are added to 93% of the gates compared to the leakage of the baseline circuit whose inputs have been subjected to the minimum leakage vector.
KW - Control point insertion
KW - leakage current reduction
KW - leakage sensitivity (LS)
KW - low power design
KW - minimum leakage vector (MLV)
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U2 - 10.1109/TCSII.2005.849026
DO - 10.1109/TCSII.2005.849026
M3 - Article
AN - SCOPUS:33748518627
SN - 1549-7747
VL - 52
SP - 496
EP - 500
JO - IEEE Transactions on Circuits and Systems II: Express Briefs
JF - IEEE Transactions on Circuits and Systems II: Express Briefs
IS - 8
ER -