An efficient compiler technique for code size reduction using reduced bit-width ISAs

Ashok Halambi, Aviral Shrivastava, Partha Biswas, Nikil Dutt, Alex Nicolau

Research output: Chapter in Book/Report/Conference proceedingConference contribution

35 Citations (Scopus)

Abstract

For many embedded applications, program code size is a critical design factor. One promising approach for reducing code size is to employ a "dual instruction set", where processor architectures support a normal (usually 32 bit) Instruction Set, and a narrow, space-efficient (usually 16 bit) Instruction Set with a limited set of opcodes and access to a limited set of registers. This future, however, requires compilers that can reduce code size by compiling for both Instruction Sets. Existing compiler techniques operate at the function-level granularity and are unable to make the trade-off between increased register pressure (resulting in more spills) and decreased code size. We present a profitability based compiler heuristic that operates at the instruction-level granularity and is able to effectively take advantage: of both Instruction Sets. We also demonstrate improved code size reduction, for the MIPS 32/16 bit ISA, using our technique. Our approach more than doubles the code size reduction achieved by existing compilers.

Original languageEnglish (US)
Title of host publicationProceedings -Design, Automation and Test in Europe, DATE
Pages402-408
Number of pages7
DOIs
StatePublished - 2002
Externally publishedYes
Event2002 Design, Automation and Test in Europe Conference and Exhibition, DATE 2002 - Paris, France
Duration: Mar 4 2002Mar 8 2002

Other

Other2002 Design, Automation and Test in Europe Conference and Exhibition, DATE 2002
CountryFrance
CityParis
Period3/4/023/8/02

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ASJC Scopus subject areas

  • Engineering(all)

Cite this

Halambi, A., Shrivastava, A., Biswas, P., Dutt, N., & Nicolau, A. (2002). An efficient compiler technique for code size reduction using reduced bit-width ISAs. In Proceedings -Design, Automation and Test in Europe, DATE (pp. 402-408). [998305] https://doi.org/10.1109/DATE.2002.998305

An efficient compiler technique for code size reduction using reduced bit-width ISAs. / Halambi, Ashok; Shrivastava, Aviral; Biswas, Partha; Dutt, Nikil; Nicolau, Alex.

Proceedings -Design, Automation and Test in Europe, DATE. 2002. p. 402-408 998305.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Halambi, A, Shrivastava, A, Biswas, P, Dutt, N & Nicolau, A 2002, An efficient compiler technique for code size reduction using reduced bit-width ISAs. in Proceedings -Design, Automation and Test in Europe, DATE., 998305, pp. 402-408, 2002 Design, Automation and Test in Europe Conference and Exhibition, DATE 2002, Paris, France, 3/4/02. https://doi.org/10.1109/DATE.2002.998305
Halambi A, Shrivastava A, Biswas P, Dutt N, Nicolau A. An efficient compiler technique for code size reduction using reduced bit-width ISAs. In Proceedings -Design, Automation and Test in Europe, DATE. 2002. p. 402-408. 998305 https://doi.org/10.1109/DATE.2002.998305
Halambi, Ashok ; Shrivastava, Aviral ; Biswas, Partha ; Dutt, Nikil ; Nicolau, Alex. / An efficient compiler technique for code size reduction using reduced bit-width ISAs. Proceedings -Design, Automation and Test in Europe, DATE. 2002. pp. 402-408
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