Abstract
For many embedded applications, program code size is a critical design factor. One promising approach for reducing code size is to employ a "dual instruction set", where processor architectures support a normal (usually 32 bit) Instruction Set, and a narrow, space-efficient (usually 16 bit) Instruction Set with a limited set of opcodes and access to a limited set of registers. This future, however, requires compilers that can reduce code size by compiling for both Instruction Sets. Existing compiler techniques operate at the function-level granularity and are unable to make the trade-off between increased register pressure (resulting in more spills) and decreased code size. We present a profitability based compiler heuristic that operates at the instruction-level granularity and is able to effectively take advantage: of both Instruction Sets. We also demonstrate improved code size reduction, for the MIPS 32/16 bit ISA, using our technique. Our approach more than doubles the code size reduction achieved by existing compilers.
Original language | English (US) |
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Title of host publication | Proceedings -Design, Automation and Test in Europe, DATE |
Pages | 402-408 |
Number of pages | 7 |
DOIs | |
State | Published - 2002 |
Externally published | Yes |
Event | 2002 Design, Automation and Test in Europe Conference and Exhibition, DATE 2002 - Paris, France Duration: Mar 4 2002 → Mar 8 2002 |
Other
Other | 2002 Design, Automation and Test in Europe Conference and Exhibition, DATE 2002 |
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Country/Territory | France |
City | Paris |
Period | 3/4/02 → 3/8/02 |
ASJC Scopus subject areas
- General Engineering