### Abstract

A data flow machine is said to be synchronized if for any vertex u in the underlying data flow graph, all inputs to vertex u arrive at the same time. An unsynchronized data flow machine with an acyclic underlying data flow graph can be transformed into a synchronized system by adding unit delay buffers to the system. This synchronization process can increase pipelining and throughout. Since the addition of delay buffers introduces hardware and area costs, it is desirable to insert the minimum number of delay buffers to synchronize a given data flow machine. Due to important applications in computer design, various delay buffer minimization problems have been studied by many researchers. Several optimal algorithms and heuristic algorithms have been proposed for slightly different models. In this paper, we introduce the concept of extensions of a directed acyclic graph to generalize and formalize several delay buffer minimization problems studied in the literature and present a polynomial time algorithm for computing the minimum delay buffer synchronization of a given data flow machine. Examples are provided to illustrate our algorithm and to show that our algorithm requires fewer delay buffers than previously published optimal algorithms for various models.

Original language | English (US) |
---|---|

Pages (from-to) | 217-233 |

Number of pages | 17 |

Journal | Journal of Combinatorial Optimization |

Volume | 4 |

Issue number | 2 |

State | Published - 2000 |

Externally published | Yes |

### Fingerprint

### Keywords

- Data flow machine
- Optimal delay buffer insertion
- VLSI technology

### ASJC Scopus subject areas

- Computational Theory and Mathematics
- Computer Science Applications
- Mathematics(all)
- Applied Mathematics
- Control and Optimization
- Discrete Mathematics and Combinatorics

### Cite this

*Journal of Combinatorial Optimization*,

*4*(2), 217-233.

**An Efficient Algorithm for Delay Buffer Minimization.** / Xue, Guoliang; Sun, Shangzhi; Du, David H C; Shi, Lojun.

Research output: Contribution to journal › Article

*Journal of Combinatorial Optimization*, vol. 4, no. 2, pp. 217-233.

}

TY - JOUR

T1 - An Efficient Algorithm for Delay Buffer Minimization

AU - Xue, Guoliang

AU - Sun, Shangzhi

AU - Du, David H C

AU - Shi, Lojun

PY - 2000

Y1 - 2000

N2 - A data flow machine is said to be synchronized if for any vertex u in the underlying data flow graph, all inputs to vertex u arrive at the same time. An unsynchronized data flow machine with an acyclic underlying data flow graph can be transformed into a synchronized system by adding unit delay buffers to the system. This synchronization process can increase pipelining and throughout. Since the addition of delay buffers introduces hardware and area costs, it is desirable to insert the minimum number of delay buffers to synchronize a given data flow machine. Due to important applications in computer design, various delay buffer minimization problems have been studied by many researchers. Several optimal algorithms and heuristic algorithms have been proposed for slightly different models. In this paper, we introduce the concept of extensions of a directed acyclic graph to generalize and formalize several delay buffer minimization problems studied in the literature and present a polynomial time algorithm for computing the minimum delay buffer synchronization of a given data flow machine. Examples are provided to illustrate our algorithm and to show that our algorithm requires fewer delay buffers than previously published optimal algorithms for various models.

AB - A data flow machine is said to be synchronized if for any vertex u in the underlying data flow graph, all inputs to vertex u arrive at the same time. An unsynchronized data flow machine with an acyclic underlying data flow graph can be transformed into a synchronized system by adding unit delay buffers to the system. This synchronization process can increase pipelining and throughout. Since the addition of delay buffers introduces hardware and area costs, it is desirable to insert the minimum number of delay buffers to synchronize a given data flow machine. Due to important applications in computer design, various delay buffer minimization problems have been studied by many researchers. Several optimal algorithms and heuristic algorithms have been proposed for slightly different models. In this paper, we introduce the concept of extensions of a directed acyclic graph to generalize and formalize several delay buffer minimization problems studied in the literature and present a polynomial time algorithm for computing the minimum delay buffer synchronization of a given data flow machine. Examples are provided to illustrate our algorithm and to show that our algorithm requires fewer delay buffers than previously published optimal algorithms for various models.

KW - Data flow machine

KW - Optimal delay buffer insertion

KW - VLSI technology

UR - http://www.scopus.com/inward/record.url?scp=0042184018&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0042184018&partnerID=8YFLogxK

M3 - Article

AN - SCOPUS:0042184018

VL - 4

SP - 217

EP - 233

JO - Journal of Combinatorial Optimization

JF - Journal of Combinatorial Optimization

SN - 1382-6905

IS - 2

ER -