An automated technique for topology and route generation of application specific on-chip interconnection networks

Krishnan Srinivasan, Karam S. Chatha, Goran Konjevod

Research output: Chapter in Book/Report/Conference proceedingConference contribution

82 Citations (Scopus)

Abstract

Network-on-chip (NoC)) has been proposed as a solution to the communication challenges of System-on-chip (SoC) design in nanoscale technologies. Application specific SoC design offers the opportunity for incorporating custom NoC architectures that are more suitable for a particular application, and do not necessarily conform to regular topologies. Custom NoC design in nanoscale technologies must address performance requirements, power consumption and physical layout considerations. This paper presents a novel three phase technique that i) generates a performance aware layout of the SoC, ii) maps the cores of the SoC to routers, and iii) generates a unique route for every trace that satisfies the performance and architectural constraints. We present an analysis of the quality of the results of the proposed technique by experimentation with realistic benchmarks.

Original languageEnglish (US)
Title of host publicationIEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
Pages231-237
Number of pages7
Volume2005
DOIs
StatePublished - 2005
EventICCAD-2005: IEEE/ACM International Conference on Computer-Aided Design, 2005 - San Jose, CA, United States
Duration: Nov 6 2005Nov 10 2005

Other

OtherICCAD-2005: IEEE/ACM International Conference on Computer-Aided Design, 2005
CountryUnited States
CitySan Jose, CA
Period11/6/0511/10/05

Fingerprint

Topology
Routers
Electric power utilization
System-on-chip
Communication
Network-on-chip

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Srinivasan, K., Chatha, K. S., & Konjevod, G. (2005). An automated technique for topology and route generation of application specific on-chip interconnection networks. In IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD (Vol. 2005, pp. 231-237). [1560070] https://doi.org/10.1109/ICCAD.2005.1560070

An automated technique for topology and route generation of application specific on-chip interconnection networks. / Srinivasan, Krishnan; Chatha, Karam S.; Konjevod, Goran.

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD. Vol. 2005 2005. p. 231-237 1560070.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Srinivasan, K, Chatha, KS & Konjevod, G 2005, An automated technique for topology and route generation of application specific on-chip interconnection networks. in IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD. vol. 2005, 1560070, pp. 231-237, ICCAD-2005: IEEE/ACM International Conference on Computer-Aided Design, 2005, San Jose, CA, United States, 11/6/05. https://doi.org/10.1109/ICCAD.2005.1560070
Srinivasan K, Chatha KS, Konjevod G. An automated technique for topology and route generation of application specific on-chip interconnection networks. In IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD. Vol. 2005. 2005. p. 231-237. 1560070 https://doi.org/10.1109/ICCAD.2005.1560070
Srinivasan, Krishnan ; Chatha, Karam S. ; Konjevod, Goran. / An automated technique for topology and route generation of application specific on-chip interconnection networks. IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD. Vol. 2005 2005. pp. 231-237
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