An automated technique for topology and route generation of application specific on-chip interconnection networks

Krishnan Srinivasan, Karam S. Chatha, Goran Konjevod

Research output: Chapter in Book/Report/Conference proceedingConference contribution

83 Scopus citations

Abstract

Network-on-chip (NoC)) has been proposed as a solution to the communication challenges of System-on-chip (SoC) design in nanoscale technologies. Application specific SoC design offers the opportunity for incorporating custom NoC architectures that are more suitable for a particular application, and do not necessarily conform to regular topologies. Custom NoC design in nanoscale technologies must address performance requirements, power consumption and physical layout considerations. This paper presents a novel three phase technique that i) generates a performance aware layout of the SoC, ii) maps the cores of the SoC to routers, and iii) generates a unique route for every trace that satisfies the performance and architectural constraints. We present an analysis of the quality of the results of the proposed technique by experimentation with realistic benchmarks.

Original languageEnglish (US)
Title of host publicationProceedings of theICCAD-2005
Subtitle of host publicationInternational Conference on Computer-Aided Design
Pages231-237
Number of pages7
DOIs
StatePublished - Dec 1 2005
EventICCAD-2005: IEEE/ACM International Conference on Computer-Aided Design, 2005 - San Jose, CA, United States
Duration: Nov 6 2005Nov 10 2005

Publication series

NameIEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
Volume2005
ISSN (Print)1092-3152

Other

OtherICCAD-2005: IEEE/ACM International Conference on Computer-Aided Design, 2005
CountryUnited States
CitySan Jose, CA
Period11/6/0511/10/05

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ASJC Scopus subject areas

  • Software
  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design

Cite this

Srinivasan, K., Chatha, K. S., & Konjevod, G. (2005). An automated technique for topology and route generation of application specific on-chip interconnection networks. In Proceedings of theICCAD-2005: International Conference on Computer-Aided Design (pp. 231-237). [1560070] (IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD; Vol. 2005). https://doi.org/10.1109/ICCAD.2005.1560070