An automated framework for accelerating numerical algorithms on reconfigurable platforms using algorithmic/architectural optimization

Jung Sub Kim, Lanping Deng, Prasanth Mangalagiri, Kevin Irick, Kanwaldeep Sobti, Mahmut Kandemir, Vijaykrishnan Narayanan, Chaitali Chakrabarti, Nikos Pitsianis, Xiaobai Sun

Research output: Contribution to journalArticle

8 Scopus citations

Abstract

This paper describes TANOR, an automated framework for designing hardware accelerators for numerical computation on reconfigurable platforms. Applications utilizing numerical algorithms on large-size data sets require high-throughput computation platforms. The focus is on N-body interaction problems which have a wide range of applications spanning from astrophysics to molecular dynamics. The TANOR design flow starts with a MATLAB description of a particular interaction function, its parameters, and certain architectural constraints specified through a graphical user interface. Subsequently, TANOR automatically generates a configuration bitstream for a target FPGA along with associated drivers and control software necessary to direct the application from a host PC. Architectural exploration is facilitated through support for fully custom fixed-point and floating-point representations in addition to standard number representations such as single-precision floating point. Moreover, TANOR enables joint exploration of algorithmic and architectural variations in realizing efficient hardware accelerators. TANOR's capabilities have been demonstrated for three different N-body interaction applications: the calculation of gravitational potential in astrophysics, the diffusion or convolution with Gaussian kernel common in image processing applications, and the force calculation with vector-valued kernel function in molecular dynamics simulation. Experimental results show that TANOR-generated hardware accelerators achieve lower resource utilization without compromising numerical accuracy, in comparison to other existing custom accelerators.

Original languageEnglish (US)
Article number5010433
Pages (from-to)1654-1667
Number of pages14
JournalIEEE Transactions on Computers
Volume58
Issue number12
DOIs
StatePublished - Dec 1 2009

Keywords

  • Algorithms implemented in hardware
  • Numerical algorithms.
  • Reconfigurable hardware
  • Signal processing systems

ASJC Scopus subject areas

  • Software
  • Theoretical Computer Science
  • Hardware and Architecture
  • Computational Theory and Mathematics

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  • Cite this

    Kim, J. S., Deng, L., Mangalagiri, P., Irick, K., Sobti, K., Kandemir, M., Narayanan, V., Chakrabarti, C., Pitsianis, N., & Sun, X. (2009). An automated framework for accelerating numerical algorithms on reconfigurable platforms using algorithmic/architectural optimization. IEEE Transactions on Computers, 58(12), 1654-1667. [5010433]. https://doi.org/10.1109/TC.2009.78