TY - JOUR
T1 - An approach to switching activity consideration during high-level, low-power design space exploration
AU - Henning, Russell
AU - Chakrabarti, Chaitali
N1 - Funding Information:
Manuscript received July 8, 1999; revised May 13, 2002. This work was supported in part by a Motorola SABA grant and in part by the National Science Foundation (NSF)/SIUCRC Center for Low Power Electronics. This paper was recommended by Associate Editor J.-T. Kong.
PY - 2002/5
Y1 - 2002/5
N2 - A novel approach is introduced that exploits characteristics of fixed-point, two's complement data in order to reduce power consumption related to switching activity. This approach is based on an intuitive switching activity model that captures the most essential data characteristics with statistical parameters. The approach is embodied in a heuristic that uses the model to systematically reduce switching activity of interconnect between data path units. The perspective provided by the model and heuristic allows efficient and intuitive high-level design space exploration. This approach is demonstrated through an example of high-level design space exploration for a low power processor dedicated to implementing the IS-54 vector-sum excited linear predictive (VSELP) speech codec. Application of the heuristic results in up to 56 % activity reduction at high energy locations in the data path and estimated processor power reduction of about 15 % on average during encoding compared to an obvious implementation.
AB - A novel approach is introduced that exploits characteristics of fixed-point, two's complement data in order to reduce power consumption related to switching activity. This approach is based on an intuitive switching activity model that captures the most essential data characteristics with statistical parameters. The approach is embodied in a heuristic that uses the model to systematically reduce switching activity of interconnect between data path units. The perspective provided by the model and heuristic allows efficient and intuitive high-level design space exploration. This approach is demonstrated through an example of high-level design space exploration for a low power processor dedicated to implementing the IS-54 vector-sum excited linear predictive (VSELP) speech codec. Application of the heuristic results in up to 56 % activity reduction at high energy locations in the data path and estimated processor power reduction of about 15 % on average during encoding compared to an obvious implementation.
KW - Design space exploration
KW - Low power
KW - Power reduction heuristic
KW - Switching activity model
KW - Vector-sum excited linear predictive (VSELP) speech codec
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U2 - 10.1109/TCSII.2002.801209
DO - 10.1109/TCSII.2002.801209
M3 - Article
AN - SCOPUS:0036583551
SN - 1057-7130
VL - 49
SP - 339
EP - 351
JO - IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
JF - IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
IS - 5
ER -