An analytical framework with bounded deflection adaptive routing for networks-on-chip

Pavel Ghosh, Arvind Ravi, Arunabha Sen

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

In a Multi-Processor System-on-Chip (MPSoC)based embedded system with Network-on-chip (NoC) as the communication architecture, routing of the communication traffic among the Processing Elements (PEs) contributes significantly to the overall latency, throughput and energy consumption. Design of an efficient routing algorithm for NoC requires a thorough understanding of the role of individual components of NoC. Simulation based studies are time-consuming and do not provide adequate insight into the design parameters for performance improvement. In this paper, we provide a framework for the analytical study of the NoC components and design an adaptive routing algorithm. Based on the traffic pattern of the communication traffic among PEs, we perform analytical studies based on network calculus and probabilistic analysis. Analytical study relates the design parameters with the worst case and average case latency and buffer requirements. Knowledge obtained from the analytical study is utilized for resource allocation of NoC, which further constitutes the design philosophy of the proposed Bounded Deflection Adaptive Routing (BDAR) algorithm. Our routing algorithm is deadlock-livelock free and efficiently reacts to link congestions. Experimental results based on simulations show that our routing algorithm performs significantly better than some existing static and dynamic routing in terms of link utilization, average and maximum end-to-end latency.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE Annual Symposium on VLSI, ISVLSI 2010
Pages363-368
Number of pages6
DOIs
StatePublished - Oct 20 2010
EventIEEE Annual Symposium on VLSI, ISVLSI 2010 - Lixouri, Kefalonia, Greece
Duration: Jul 5 2010Jul 7 2010

Publication series

NameProceedings - IEEE Annual Symposium on VLSI, ISVLSI 2010

Other

OtherIEEE Annual Symposium on VLSI, ISVLSI 2010
CountryGreece
CityLixouri, Kefalonia
Period7/5/107/7/10

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ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Ghosh, P., Ravi, A., & Sen, A. (2010). An analytical framework with bounded deflection adaptive routing for networks-on-chip. In Proceedings - IEEE Annual Symposium on VLSI, ISVLSI 2010 (pp. 363-368). [5572804] (Proceedings - IEEE Annual Symposium on VLSI, ISVLSI 2010). https://doi.org/10.1109/ISVLSI.2010.90