An analytical approach to efficient circuit variability analysis in scaled CMOS design

Samatha Gummalla, Anupama R. Subramaniam, Yu Cao, Chaitali Chakrabarti

Research output: Chapter in Book/Report/Conference proceedingConference contribution

11 Citations (Scopus)

Abstract

CMOS scaling has led to increasingly high variability in device and circuit performance. To improve design robustness, it is important to consider variation in the design flow. In this paper a closed-form solution is proposed to predict the variability in gate timing, which significantly reduces computation cost in statistical analysis. The proposed model covers both nominal delay and its variability across a wide range of device sizes, load capacitances and input transition times. Stack effect, such as that in NAND and NOR gates, is taken into account thereby making the model sensitive to the switching patterns. For ISCAS'85 benchmark circuits, implemented using a 45nm library, the model demonstrates high accuracy with less than 3.5% error for nominal delay and within 5ps variation of the critical path. Finally, use of the proposed model in design flow is demonstrated for setup time violations.

Original languageEnglish (US)
Title of host publicationProceedings - International Symposium on Quality Electronic Design, ISQED
Pages641-647
Number of pages7
DOIs
StatePublished - 2012
Event13th International Symposium on Quality Electronic Design, ISQED 2012 - Santa Clara, CA, United States
Duration: Mar 19 2012Mar 21 2012

Other

Other13th International Symposium on Quality Electronic Design, ISQED 2012
CountryUnited States
CitySanta Clara, CA
Period3/19/123/21/12

Fingerprint

Electric network analysis
Networks (circuits)
Statistical methods
Capacitance
Costs

Keywords

  • critical path
  • statistical analysis
  • Timing model
  • variation

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality

Cite this

Gummalla, S., Subramaniam, A. R., Cao, Y., & Chakrabarti, C. (2012). An analytical approach to efficient circuit variability analysis in scaled CMOS design. In Proceedings - International Symposium on Quality Electronic Design, ISQED (pp. 641-647). [6187560] https://doi.org/10.1109/ISQED.2012.6187560

An analytical approach to efficient circuit variability analysis in scaled CMOS design. / Gummalla, Samatha; Subramaniam, Anupama R.; Cao, Yu; Chakrabarti, Chaitali.

Proceedings - International Symposium on Quality Electronic Design, ISQED. 2012. p. 641-647 6187560.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Gummalla, S, Subramaniam, AR, Cao, Y & Chakrabarti, C 2012, An analytical approach to efficient circuit variability analysis in scaled CMOS design. in Proceedings - International Symposium on Quality Electronic Design, ISQED., 6187560, pp. 641-647, 13th International Symposium on Quality Electronic Design, ISQED 2012, Santa Clara, CA, United States, 3/19/12. https://doi.org/10.1109/ISQED.2012.6187560
Gummalla S, Subramaniam AR, Cao Y, Chakrabarti C. An analytical approach to efficient circuit variability analysis in scaled CMOS design. In Proceedings - International Symposium on Quality Electronic Design, ISQED. 2012. p. 641-647. 6187560 https://doi.org/10.1109/ISQED.2012.6187560
Gummalla, Samatha ; Subramaniam, Anupama R. ; Cao, Yu ; Chakrabarti, Chaitali. / An analytical approach to efficient circuit variability analysis in scaled CMOS design. Proceedings - International Symposium on Quality Electronic Design, ISQED. 2012. pp. 641-647
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