CMOS scaling has led to increasingly high variability in device and circuit performance. To improve design robustness, it is important to consider variation in the design flow. In this paper a closed-form solution is proposed to predict the variability in gate timing, which significantly reduces computation cost in statistical analysis. The proposed model covers both nominal delay and its variability across a wide range of device sizes, load capacitances and input transition times. Stack effect, such as that in NAND and NOR gates, is taken into account thereby making the model sensitive to the switching patterns. For ISCAS'85 benchmark circuits, implemented using a 45nm library, the model demonstrates high accuracy with less than 3.5% error for nominal delay and within 5ps variation of the critical path. Finally, use of the proposed model in design flow is demonstrated for setup time violations.