TY - JOUR
T1 - An analytical approach for network-on-chip performance analysis
AU - Ogras, Umit Y.
AU - Bogdan, Paul
AU - Marculescu, Radu
N1 - Funding Information:
The authors gratefully acknowledge the financial support from the Semiconductor Research Corporation (SRC) and National Science Foundation (NSF). Any opinions, findings, conclusions, or recommendations expressed in this material are those of the authors and do not necessarily reflect the views of the National Science Foundation. P. Bogdan also acknowledges the financial support received through a Fellowship from the Roberto Rocca Education Program.
Funding Information:
Manuscript received October 19, 2009; revised February 15, 2010 and April 27, 2010; accepted July 12, 2010. Date of current version November 19, 2010. This work was supported in part by the Semiconductor Research Corporation, under Grant 2008-HJ-1823, and in part by the National Science Foundation, under Grants CCF-0702420 and CCF-0916752. This paper was presented in part as “Analytical router modeling for networks-on-chip performance analysis” at the Proceedings of the Design, Automation and Test in Europe Conference, Nice, France, April 2007. This paper was recommended by Associate Editor L. Benini.
PY - 2010/12
Y1 - 2010/12
N2 - Networks-on-chip (NoCs) have recently emerged as a scalable alternative to classical bus and point-to-point architectures. To date, performance evaluation of NoC designs is largely based on simulation which, besides being extremely slow, provides little insight on how different design parameters affect the actual network performance. Therefore, it is practically impossible to use simulation for optimization purposes. In this paper, we present a mathematical model for on-chip routers and utilize this new model for NoC performance analysis. The proposed model can be used not only to obtain fast and accurate performance estimates, but also to guide the NoC design process within an optimization loop. The accuracy of our approach and its practical use is illustrated through extensive simulation results.
AB - Networks-on-chip (NoCs) have recently emerged as a scalable alternative to classical bus and point-to-point architectures. To date, performance evaluation of NoC designs is largely based on simulation which, besides being extremely slow, provides little insight on how different design parameters affect the actual network performance. Therefore, it is practically impossible to use simulation for optimization purposes. In this paper, we present a mathematical model for on-chip routers and utilize this new model for NoC performance analysis. The proposed model can be used not only to obtain fast and accurate performance estimates, but also to guide the NoC design process within an optimization loop. The accuracy of our approach and its practical use is illustrated through extensive simulation results.
KW - Multiprocessor systems-on-chip (MPSoCs)
KW - networks-on-chip (NoCs)
KW - performance analysis
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U2 - 10.1109/TCAD.2010.2061613
DO - 10.1109/TCAD.2010.2061613
M3 - Article
AN - SCOPUS:78649386126
SN - 0278-0070
VL - 29
SP - 2001
EP - 2013
JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IS - 12
M1 - 5621037
ER -