An all-digital programmable digitally-controlled-oscillator (DCO) for digital wireless applications

S. R. Abdollahi; Sayfe Kiaei; Bertan Bakkaloglu; S. M. Fakhraie; R. Anvari; S. E. Abdollahi

An all-digital programmable digitally-controlled-oscillator (DCO) for digital wireless applications

S. R. Abdollahi, Sayfe Kiaei, Bertan Bakkaloglu, S. M. Fakhraie, R. Anvari, S. E. Abdollahi

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

A programmable digitally controlled oscillator (DCO) core is mapped on an Altera MAX9400 CPLD that can be used for clock recovery circuit of a 2.4 - 19.2 Kb/sec Gaussian Minimum Shift Keying (GMSK) demodulator. This architecture is suitable for digital wireless transceivers that use different bands for transmit and receive modes, such as SM and DECT. Linearity and phase noise of the DCO is analyzed at different oscillation frequencies. Thermal drift and power supply level sensitivity is characterized. This architecture can be used for higher frequencies using faster FPGA devices or by implementing it on a deep-submicron process.

Original language	English (US)
Title of host publication	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	4
State	Published - 2002
Event	2002 IEEE International Symposium on Circuits and Systems - Phoenix, AZ, United States Duration: May 26 2002 → May 29 2002

Other

Other	2002 IEEE International Symposium on Circuits and Systems
Country/Territory	United States
City	Phoenix, AZ
Period	5/26/02 → 5/29/02

ASJC Scopus subject areas

Electrical and Electronic Engineering
Electronic, Optical and Magnetic Materials

Cite this

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title = "An all-digital programmable digitally-controlled-oscillator (DCO) for digital wireless applications",

abstract = "A programmable digitally controlled oscillator (DCO) core is mapped on an Altera MAX9400 CPLD that can be used for clock recovery circuit of a 2.4 - 19.2 Kb/sec Gaussian Minimum Shift Keying (GMSK) demodulator. This architecture is suitable for digital wireless transceivers that use different bands for transmit and receive modes, such as SM and DECT. Linearity and phase noise of the DCO is analyzed at different oscillation frequencies. Thermal drift and power supply level sensitivity is characterized. This architecture can be used for higher frequencies using faster FPGA devices or by implementing it on a deep-submicron process.",

author = "Abdollahi, {S. R.} and Sayfe Kiaei and Bertan Bakkaloglu and Fakhraie, {S. M.} and R. Anvari and Abdollahi, {S. E.}",

year = "2002",

language = "English (US)",

volume = "4",

booktitle = "Proceedings - IEEE International Symposium on Circuits and Systems",

note = "2002 IEEE International Symposium on Circuits and Systems ; Conference date: 26-05-2002 Through 29-05-2002",

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T1 - An all-digital programmable digitally-controlled-oscillator (DCO) for digital wireless applications

AU - Abdollahi, S. R.

AU - Kiaei, Sayfe

AU - Bakkaloglu, Bertan

AU - Fakhraie, S. M.

AU - Anvari, R.

AU - Abdollahi, S. E.

PY - 2002

Y1 - 2002

N2 - A programmable digitally controlled oscillator (DCO) core is mapped on an Altera MAX9400 CPLD that can be used for clock recovery circuit of a 2.4 - 19.2 Kb/sec Gaussian Minimum Shift Keying (GMSK) demodulator. This architecture is suitable for digital wireless transceivers that use different bands for transmit and receive modes, such as SM and DECT. Linearity and phase noise of the DCO is analyzed at different oscillation frequencies. Thermal drift and power supply level sensitivity is characterized. This architecture can be used for higher frequencies using faster FPGA devices or by implementing it on a deep-submicron process.

AB - A programmable digitally controlled oscillator (DCO) core is mapped on an Altera MAX9400 CPLD that can be used for clock recovery circuit of a 2.4 - 19.2 Kb/sec Gaussian Minimum Shift Keying (GMSK) demodulator. This architecture is suitable for digital wireless transceivers that use different bands for transmit and receive modes, such as SM and DECT. Linearity and phase noise of the DCO is analyzed at different oscillation frequencies. Thermal drift and power supply level sensitivity is characterized. This architecture can be used for higher frequencies using faster FPGA devices or by implementing it on a deep-submicron process.

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M3 - Conference contribution

AN - SCOPUS:0036290950

VL - 4

BT - Proceedings - IEEE International Symposium on Circuits and Systems

T2 - 2002 IEEE International Symposium on Circuits and Systems

Y2 - 26 May 2002 through 29 May 2002

ER -

An all-digital programmable digitally-controlled-oscillator (DCO) for digital wireless applications

Abstract

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ASJC Scopus subject areas

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