An ADC-BiST scheme using sequential code analysis

Erdem S. Erdogan, Sule Ozev

Research output: Chapter in Book/Report/Conference proceedingConference contribution

17 Scopus citations

Abstract

This paper presents a built-in self-test (BiST) scheme for analog to digital converters (ADC) based on a linear ramp generator and efficient output analysis. The proposed analysis method is an alternative to histogram based analysis techniques to provide test time improvements, especially when the resources are scarce. In addition to the measurement of DNL and INL non-monotonic behavior can also be detected with the proposed technique. We present two implementation options based on how much on-chip resources are available. The ramp generator has a high linearity over a full-scale range of IV and the generated ramp signal is capable of testing 13 - bit ADCs. The circuit implementation of the ramp generator utilizes a feedback configuration to improve the linearity having an area of 0.017mm2 in 0.5μm process.

Original languageEnglish (US)
Title of host publicationProceedings -Design, Automation and Test in Europe, DATE
Pages713-718
Number of pages6
DOIs
Publication statusPublished - 2007
Externally publishedYes
Event2007 Design, Automation and Test in Europe Conference and Exhibition - Nice Acropolis, France
Duration: Apr 16 2007Apr 20 2007

Other

Other2007 Design, Automation and Test in Europe Conference and Exhibition
CountryFrance
CityNice Acropolis
Period4/16/074/20/07

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ASJC Scopus subject areas

  • Engineering(all)

Cite this

Erdogan, E. S., & Ozev, S. (2007). An ADC-BiST scheme using sequential code analysis. In Proceedings -Design, Automation and Test in Europe, DATE (pp. 713-718). [4211884] https://doi.org/10.1109/DATE.2007.364679