An 8-Bit Compressive Sensing ADC with 4-GS/s Equivalent Speed Utilizing Self-Timed Pipeline SAR-Binary-Search

Boyu Hu, Fengbo Ren, Zuow Zun Chen, Xicheng Jiang, Mau Chung Frank Chang

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

This brief presents a 65-nm CMOS single-channel 8-bit ADC compatible for energy-efficient high-speed compressive sensing (CS) and Nyquist sampling (NS). A self-Timed pipeline two-stage SAR-binary-search architecture is proposed and integrated with a 4-GHz random-matrix clock generator, enabling a physical sampling speed up to 500 MS/s with 40.2-dB SNDR in NS-mode and an equivalent speed up to 4 GS/s with 36.2-dB SNDR in CS-mode, leading to FOMs of 239 fJ/conversion-step and 71 fJ/conversion-step, respectively. A passive-charge-sharing with open-loop residue-Amplifier technique is proposed to boost the maximum physical sampling speed and the equivalent CS acquisition bandwidth. A reference-voltage fitting calibration scheme is applied to predistort interstage errors.

Original languageEnglish (US)
Article number7426415
Pages (from-to)934-938
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Volume63
Issue number10
DOIs
StatePublished - Oct 1 2016

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Pipelines
Sampling
Clocks
Calibration
Bandwidth
Electric potential

Keywords

  • ADC
  • compressive sensing (CS)
  • SAR-binary-search (BS)
  • self-Timed pipeline

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

An 8-Bit Compressive Sensing ADC with 4-GS/s Equivalent Speed Utilizing Self-Timed Pipeline SAR-Binary-Search. / Hu, Boyu; Ren, Fengbo; Chen, Zuow Zun; Jiang, Xicheng; Chang, Mau Chung Frank.

In: IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 63, No. 10, 7426415, 01.10.2016, p. 934-938.

Research output: Contribution to journalArticle

@article{25452e76e91245a98aee35f29960a59c,
title = "An 8-Bit Compressive Sensing ADC with 4-GS/s Equivalent Speed Utilizing Self-Timed Pipeline SAR-Binary-Search",
abstract = "This brief presents a 65-nm CMOS single-channel 8-bit ADC compatible for energy-efficient high-speed compressive sensing (CS) and Nyquist sampling (NS). A self-Timed pipeline two-stage SAR-binary-search architecture is proposed and integrated with a 4-GHz random-matrix clock generator, enabling a physical sampling speed up to 500 MS/s with 40.2-dB SNDR in NS-mode and an equivalent speed up to 4 GS/s with 36.2-dB SNDR in CS-mode, leading to FOMs of 239 fJ/conversion-step and 71 fJ/conversion-step, respectively. A passive-charge-sharing with open-loop residue-Amplifier technique is proposed to boost the maximum physical sampling speed and the equivalent CS acquisition bandwidth. A reference-voltage fitting calibration scheme is applied to predistort interstage errors.",
keywords = "ADC, compressive sensing (CS), SAR-binary-search (BS), self-Timed pipeline",
author = "Boyu Hu and Fengbo Ren and Chen, {Zuow Zun} and Xicheng Jiang and Chang, {Mau Chung Frank}",
year = "2016",
month = "10",
day = "1",
doi = "10.1109/TCSII.2016.2538378",
language = "English (US)",
volume = "63",
pages = "934--938",
journal = "IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing",
issn = "1549-7747",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "10",

}

TY - JOUR

T1 - An 8-Bit Compressive Sensing ADC with 4-GS/s Equivalent Speed Utilizing Self-Timed Pipeline SAR-Binary-Search

AU - Hu, Boyu

AU - Ren, Fengbo

AU - Chen, Zuow Zun

AU - Jiang, Xicheng

AU - Chang, Mau Chung Frank

PY - 2016/10/1

Y1 - 2016/10/1

N2 - This brief presents a 65-nm CMOS single-channel 8-bit ADC compatible for energy-efficient high-speed compressive sensing (CS) and Nyquist sampling (NS). A self-Timed pipeline two-stage SAR-binary-search architecture is proposed and integrated with a 4-GHz random-matrix clock generator, enabling a physical sampling speed up to 500 MS/s with 40.2-dB SNDR in NS-mode and an equivalent speed up to 4 GS/s with 36.2-dB SNDR in CS-mode, leading to FOMs of 239 fJ/conversion-step and 71 fJ/conversion-step, respectively. A passive-charge-sharing with open-loop residue-Amplifier technique is proposed to boost the maximum physical sampling speed and the equivalent CS acquisition bandwidth. A reference-voltage fitting calibration scheme is applied to predistort interstage errors.

AB - This brief presents a 65-nm CMOS single-channel 8-bit ADC compatible for energy-efficient high-speed compressive sensing (CS) and Nyquist sampling (NS). A self-Timed pipeline two-stage SAR-binary-search architecture is proposed and integrated with a 4-GHz random-matrix clock generator, enabling a physical sampling speed up to 500 MS/s with 40.2-dB SNDR in NS-mode and an equivalent speed up to 4 GS/s with 36.2-dB SNDR in CS-mode, leading to FOMs of 239 fJ/conversion-step and 71 fJ/conversion-step, respectively. A passive-charge-sharing with open-loop residue-Amplifier technique is proposed to boost the maximum physical sampling speed and the equivalent CS acquisition bandwidth. A reference-voltage fitting calibration scheme is applied to predistort interstage errors.

KW - ADC

KW - compressive sensing (CS)

KW - SAR-binary-search (BS)

KW - self-Timed pipeline

UR - http://www.scopus.com/inward/record.url?scp=84989345423&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84989345423&partnerID=8YFLogxK

U2 - 10.1109/TCSII.2016.2538378

DO - 10.1109/TCSII.2016.2538378

M3 - Article

AN - SCOPUS:84989345423

VL - 63

SP - 934

EP - 938

JO - IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

JF - IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

SN - 1549-7747

IS - 10

M1 - 7426415

ER -