An 8-Bit Compressive Sensing ADC with 4-GS/s Equivalent Speed Utilizing Self-Timed Pipeline SAR-Binary-Search

Boyu Hu; Fengbo Ren; Zuow Zun Chen; Xicheng Jiang; Mau Chung Frank Chang

doi:10.1109/TCSII.2016.2538378

An 8-Bit Compressive Sensing ADC with 4-GS/s Equivalent Speed Utilizing Self-Timed Pipeline SAR-Binary-Search

Boyu Hu, Fengbo Ren, Zuow Zun Chen, Xicheng Jiang, Mau Chung Frank Chang

Research output: Contribution to journal › Article › peer-review

3 Scopus citations

Abstract

This brief presents a 65-nm CMOS single-channel 8-bit ADC compatible for energy-efficient high-speed compressive sensing (CS) and Nyquist sampling (NS). A self-Timed pipeline two-stage SAR-binary-search architecture is proposed and integrated with a 4-GHz random-matrix clock generator, enabling a physical sampling speed up to 500 MS/s with 40.2-dB SNDR in NS-mode and an equivalent speed up to 4 GS/s with 36.2-dB SNDR in CS-mode, leading to FOMs of 239 fJ/conversion-step and 71 fJ/conversion-step, respectively. A passive-charge-sharing with open-loop residue-Amplifier technique is proposed to boost the maximum physical sampling speed and the equivalent CS acquisition bandwidth. A reference-voltage fitting calibration scheme is applied to predistort interstage errors.

Original language	English (US)
Article number	7426415
Pages (from-to)	934-938
Number of pages	5
Journal	IEEE Transactions on Circuits and Systems II: Express Briefs
Volume	63
Issue number	10
DOIs	https://doi.org/10.1109/TCSII.2016.2538378
State	Published - Oct 1 2016

Keywords

ADC
compressive sensing (CS)
SAR-binary-search (BS)
self-Timed pipeline

ASJC Scopus subject areas

Electrical and Electronic Engineering

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An 8-Bit Compressive Sensing ADC with 4-GS/s Equivalent Speed Utilizing Self-Timed Pipeline SAR-Binary-Search. / Hu, Boyu; Ren, Fengbo; Chen, Zuow Zun; Jiang, Xicheng; Chang, Mau Chung Frank.

In: IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 63, No. 10, 7426415, 01.10.2016, p. 934-938.

Research output: Contribution to journal › Article › peer-review

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abstract = "This brief presents a 65-nm CMOS single-channel 8-bit ADC compatible for energy-efficient high-speed compressive sensing (CS) and Nyquist sampling (NS). A self-Timed pipeline two-stage SAR-binary-search architecture is proposed and integrated with a 4-GHz random-matrix clock generator, enabling a physical sampling speed up to 500 MS/s with 40.2-dB SNDR in NS-mode and an equivalent speed up to 4 GS/s with 36.2-dB SNDR in CS-mode, leading to FOMs of 239 fJ/conversion-step and 71 fJ/conversion-step, respectively. A passive-charge-sharing with open-loop residue-Amplifier technique is proposed to boost the maximum physical sampling speed and the equivalent CS acquisition bandwidth. A reference-voltage fitting calibration scheme is applied to predistort interstage errors.",

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AB - This brief presents a 65-nm CMOS single-channel 8-bit ADC compatible for energy-efficient high-speed compressive sensing (CS) and Nyquist sampling (NS). A self-Timed pipeline two-stage SAR-binary-search architecture is proposed and integrated with a 4-GHz random-matrix clock generator, enabling a physical sampling speed up to 500 MS/s with 40.2-dB SNDR in NS-mode and an equivalent speed up to 4 GS/s with 36.2-dB SNDR in CS-mode, leading to FOMs of 239 fJ/conversion-step and 71 fJ/conversion-step, respectively. A passive-charge-sharing with open-loop residue-Amplifier technique is proposed to boost the maximum physical sampling speed and the equivalent CS acquisition bandwidth. A reference-voltage fitting calibration scheme is applied to predistort interstage errors.

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An 8-Bit Compressive Sensing ADC with 4-GS/s Equivalent Speed Utilizing Self-Timed Pipeline SAR-Binary-Search

Abstract

Keywords

ASJC Scopus subject areas

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