An 8-Bit Compressive Sensing ADC with 4-GS/s Equivalent Speed Utilizing Self-Timed Pipeline SAR-Binary-Search

Boyu Hu, Fengbo Ren, Zuow Zun Chen, Xicheng Jiang, Mau Chung Frank Chang

Research output: Contribution to journalArticle

2 Scopus citations

Abstract

This brief presents a 65-nm CMOS single-channel 8-bit ADC compatible for energy-efficient high-speed compressive sensing (CS) and Nyquist sampling (NS). A self-Timed pipeline two-stage SAR-binary-search architecture is proposed and integrated with a 4-GHz random-matrix clock generator, enabling a physical sampling speed up to 500 MS/s with 40.2-dB SNDR in NS-mode and an equivalent speed up to 4 GS/s with 36.2-dB SNDR in CS-mode, leading to FOMs of 239 fJ/conversion-step and 71 fJ/conversion-step, respectively. A passive-charge-sharing with open-loop residue-Amplifier technique is proposed to boost the maximum physical sampling speed and the equivalent CS acquisition bandwidth. A reference-voltage fitting calibration scheme is applied to predistort interstage errors.

Original languageEnglish (US)
Article number7426415
Pages (from-to)934-938
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Volume63
Issue number10
DOIs
StatePublished - Oct 1 2016

Keywords

  • ADC
  • compressive sensing (CS)
  • SAR-binary-search (BS)
  • self-Timed pipeline

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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