TY - JOUR
T1 - Algorithmic Optimization of Thermal and Power Management for Heterogeneous Mobile Platforms
AU - Bhat, Ganapati
AU - Singla, Gaurav
AU - Unver, Ali K.
AU - Ogras, Umit
N1 - Funding Information:
Manuscript received May 5, 2017; revised August 5, 2017 and October 10, 2017; accepted October 11, 2017. Date of publication November 27, 2017; date of current version February 22, 2018. This work was supported in part by Strategic CAD Labs, Intel Corporation, Semiconductor Research Corporation under Grant 2721.001 and in part by the National Science Foundation under Grant CNS-1526562. (Corresponding author: Ganapati Bhat.) G. Bhat and U. Y. Ogras are with the School of Electrical, Computer and Energy Engineering, Arizona State University, Tempe, AZ 85287 USA (e-mail: gmbhat@asu.edu; umit@asu.edu).
Publisher Copyright:
© 1993-2012 IEEE.
PY - 2017/11/26
Y1 - 2017/11/26
N2 - State-of-the-art mobile platforms are powered by heterogeneous system-on-chips that integrate multiple CPU cores, a GPU, and many specialized processors. Competitive performance on these platforms comes at the expense of increased power density due to their small form factor. Consequently, the skin temperature, which can degrade the experience, becomes a limiting factor. Since using a fan is not a viable solution for hand-held devices, there is a strong need for dynamic thermal and power management (DTPM) algorithms that can regulate temperature with minimal performance impact. This paper presents a DTPM algorithm, which uses a practical temperature prediction methodology based on system identification. The proposed algorithm dynamically computes a power budget using the predicted temperature. This budget is used to throttle the frequency and number of cores to avoid temperature violations with minimal impact on the system performance. Our experimental measurements on two different octa-core big.LITTLE processors and common Android applications demonstrate that the proposed technique predicts the temperature with less than 5% error across all benchmarks. Using this prediction, the proposed DTPM algorithm successfully regulates the maximum temperature and decreases the temperature violations by one order of magnitude while also reducing the total power consumption on average by 7% compared with the default solution.
AB - State-of-the-art mobile platforms are powered by heterogeneous system-on-chips that integrate multiple CPU cores, a GPU, and many specialized processors. Competitive performance on these platforms comes at the expense of increased power density due to their small form factor. Consequently, the skin temperature, which can degrade the experience, becomes a limiting factor. Since using a fan is not a viable solution for hand-held devices, there is a strong need for dynamic thermal and power management (DTPM) algorithms that can regulate temperature with minimal performance impact. This paper presents a DTPM algorithm, which uses a practical temperature prediction methodology based on system identification. The proposed algorithm dynamically computes a power budget using the predicted temperature. This budget is used to throttle the frequency and number of cores to avoid temperature violations with minimal impact on the system performance. Our experimental measurements on two different octa-core big.LITTLE processors and common Android applications demonstrate that the proposed technique predicts the temperature with less than 5% error across all benchmarks. Using this prediction, the proposed DTPM algorithm successfully regulates the maximum temperature and decreases the temperature violations by one order of magnitude while also reducing the total power consumption on average by 7% compared with the default solution.
KW - Dynamic power management
KW - heterogeneous computing
KW - multicore architectures
KW - multiprocessor systems-on-chip (MPSoCs)
KW - thermal management
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U2 - 10.1109/TVLSI.2017.2770163
DO - 10.1109/TVLSI.2017.2770163
M3 - Article
AN - SCOPUS:85037669017
SN - 1063-8210
VL - 26
SP - 544
EP - 557
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IS - 3
ER -