TY - GEN
T1 - AI Computing in Light of 2.5D Interconnect Roadmap
T2 - 2022 International Electron Devices Meeting, IEDM 2022
AU - Wang, Zhenyu
AU - Nair, Gopikrishnan Raveendran
AU - Krishnan, Gokul
AU - Mandal, Sumit K.
AU - Cherian, Ninoo
AU - Seo, Jae Sun
AU - Chakrabarti, Chaitali
AU - Ogras, Umit
AU - Cao, Yu
N1 - Funding Information:
This work was partially supported by C-BRIC, one of six centers in JUMP, a Semiconductor Research Corporation (SRC) program sponsored by DARPA.
Publisher Copyright:
© 2022 IEEE.
PY - 2022
Y1 - 2022
N2 - The demands on bandwidth, latency and energy efficiency are ever increasing in AI computing. Chiplets, connected by 2. 5D interconnect, promise a scalable platform to meet such needs. We present a pathfinding study to bridge AI algorithms with the chiplet architecture, covering in memory computing (IMC), network-on-package (NoP), and heterogeneous architecture. This study is enabled by our newly developed benchmarking tool, SIAM. We perform simulations on representative algorithms (DNNs, transformers and GCNs). Particular contributions include: (1) A roadmap of 2. 5D interconnect for technological exploration; (2) A generic mapping and optimization methodology that reveals various bandwidth needs in AI computing, where the evolution of 2.5D interconnect can or cannot support; (3) A big-little chiplet architecture that matches the non-uniform nature of AI algorithms and achieves >100× improvement in EDP. Overall, heterogeneous big-little chiplets with 2. 5D interconnect advance AI computing to the next level of data movement and computing efficiency.
AB - The demands on bandwidth, latency and energy efficiency are ever increasing in AI computing. Chiplets, connected by 2. 5D interconnect, promise a scalable platform to meet such needs. We present a pathfinding study to bridge AI algorithms with the chiplet architecture, covering in memory computing (IMC), network-on-package (NoP), and heterogeneous architecture. This study is enabled by our newly developed benchmarking tool, SIAM. We perform simulations on representative algorithms (DNNs, transformers and GCNs). Particular contributions include: (1) A roadmap of 2. 5D interconnect for technological exploration; (2) A generic mapping and optimization methodology that reveals various bandwidth needs in AI computing, where the evolution of 2.5D interconnect can or cannot support; (3) A big-little chiplet architecture that matches the non-uniform nature of AI algorithms and achieves >100× improvement in EDP. Overall, heterogeneous big-little chiplets with 2. 5D interconnect advance AI computing to the next level of data movement and computing efficiency.
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U2 - 10.1109/IEDM45625.2022.10019406
DO - 10.1109/IEDM45625.2022.10019406
M3 - Conference contribution
AN - SCOPUS:85147505612
T3 - Technical Digest - International Electron Devices Meeting, IEDM
SP - 2361
EP - 2364
BT - 2022 International Electron Devices Meeting, IEDM 2022
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 3 December 2022 through 7 December 2022
ER -