Aging statistics based on trapping/detrapping: Compact modeling and silicon validation

Design for reliability is an increasingly important design step at advanced technology nodes. Aggressive scaling has brought forth reliability issues, such as negative bias temperature instability (NBTI). The aging process due to NBTI exhibits a significant amount of variability for a single device and for multiple devices. As a result, long-term reliability prediction from short-term stress measurement becomes dramatically challenging. With increasing reliability concerns, accurate statistical aging prediction is essential in order to develop robust guard banding and protection strategies during the design stage. To develop an accurate long-term prediction method under variations, this paper first collects statistical device data from a 65-nm test chip with a resolution of 0.2 mV in the threshold voltage V_th measurement. Comparing the aging prediction from short-term stress data (< 20 k second) with the direct long-term measurement (up to 200 k second), we conclude that: 1) the aging in a pMOS device follows logarithmic time dependence rather than conventional power law; 2) a traditional tⁿ model overestimates the aging rate and the variance for long-term behavior; and 3) a trapping/detrapping (TD)-based log(t) model correctly captures the aging variability due to the randomness in the number of initial available traps, and it accurately predicts the mean and the variance of the V_th shift. These results guide the development of a new aging model for robust long-term lifetime prediction. Furthermore, the effectiveness of the new log(t) model is evaluated by the statistical aging data from 65-nm ring oscillators. Compared with previous models, the new log (t) model based on the TD theory well captures the mean and the variance at the circuit level.