Aggregating processor free time for energy reduction

Aviral Shrivastava, Eugene Earlie, Nikil Dutt, Alex Nicolau

Research output: Chapter in Book/Report/Conference proceedingConference contribution

11 Scopus citations

Abstract

Even after carefully tuning the memory characteristics to the application properties and the processor speed, during the execution of real applications there are times when the processor stalls, waiting for data from the memory. Processor stall can be used to increase the throughput by temporarily switching to a different thread of execution, or reduce the power and energy consumption by temporarily switching the processor to low-power mode. However, any such technique has a performance overhead in terms of switching time. Even though over the execution of an application the processor is stalled for a considerable amount of time, each stall duration is too small to profitably perform any state switch. In this paper, we present code transformations to aggregate processor free time. Our experiments on the Intel XScale and Stream kernels show that up to 50,000 processor cycles can be aggregated, and used to profitably switch the processor to low-power mode. We further show that our code transformations can switch the processor to low-power mode for up to 75% of kernel runtime, achieving up to 18% of processor energy savings on multimedia applications. Our technique requires minimal architectural modifications and incurs negligible (< 1%) performance loss.

Original languageEnglish (US)
Title of host publicationCODES+ISSS 2005 - International Conference on Hardware/Software Codesign and Systems Synthesis
PublisherAssociation for Computing Machinery
Pages154-159
Number of pages6
ISBN (Print)1595931619, 9781595931610
DOIs
StatePublished - Jan 1 2005
Event3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and Systems Synthesis CODES+ISSS 2005 - Jersey City, NJ, United States
Duration: Sep 18 2005Sep 21 2005

Publication series

NameCODES+ISSS 2005 - International Conference on Hardware/Software Codesign and System Synthesis

Other

Other3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and Systems Synthesis CODES+ISSS 2005
CountryUnited States
CityJersey City, NJ
Period9/18/059/21/05

Keywords

  • Aggregation
  • Clock Gating
  • Code Transformation
  • Embedded Systems
  • Energy Reduction
  • Processor Free Time

ASJC Scopus subject areas

  • Engineering(all)

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  • Cite this

    Shrivastava, A., Earlie, E., Dutt, N., & Nicolau, A. (2005). Aggregating processor free time for energy reduction. In CODES+ISSS 2005 - International Conference on Hardware/Software Codesign and Systems Synthesis (pp. 154-159). (CODES+ISSS 2005 - International Conference on Hardware/Software Codesign and System Synthesis). Association for Computing Machinery. https://doi.org/10.1145/1084834.1084876