Advanced encryption system with dynamic pipeline reconfiguration for minimum energy operation

Srivatsan Chellappa, Chandarasekaran Ramamurthy, Vinay Vashishtha, Lawrence T. Clark

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Scopus citations

Abstract

Power dissipation is a major concern in sub-nanometer IC designs with technology scaling pushing towards higher clock frequencies. Techniques such as dynamic voltage (and frequency) scaling (DVS) to minimize power while providing good throughput have become commonplace. This paper presents a fully pipelined 256-bit key advanced encryption system (AES) design implemented with power-saving pulse-clocked latches as pipeline flip-flops that supports pipeline collapse, whereby pipeline stages can be unified by making stage latches transparent. The design is fabricated on a foundry 90-nm low standby power process. Measured results show the design is capable of 64 Gb/s encryption, limited by the I/O speed. A 7.6% decrease in the energy per operation beyond DVS power reduction using pipeline stage unification (PSU) is obtained.

Original languageEnglish (US)
Title of host publicationProceedings - International Symposium on Quality Electronic Design, ISQED
PublisherIEEE Computer Society
Pages201-206
Number of pages6
Volume2015-April
ISBN (Print)9781479975815
DOIs
StatePublished - Apr 13 2015
Event16th International Symposium on Quality Electronic Design, ISQED 2015 - Santa Clara, United States
Duration: Mar 2 2015Mar 4 2015

Other

Other16th International Symposium on Quality Electronic Design, ISQED 2015
CountryUnited States
CitySanta Clara
Period3/2/153/4/15

Keywords

  • advanced encryption standard
  • dynamic voltage scaling
  • IC power
  • pipeline stage unification
  • pulse latch

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality

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  • Cite this

    Chellappa, S., Ramamurthy, C., Vashishtha, V., & Clark, L. T. (2015). Advanced encryption system with dynamic pipeline reconfiguration for minimum energy operation. In Proceedings - International Symposium on Quality Electronic Design, ISQED (Vol. 2015-April, pp. 201-206). [7085425] IEEE Computer Society. https://doi.org/10.1109/ISQED.2015.7085425