TY - GEN
T1 - Advanced encryption system with dynamic pipeline reconfiguration for minimum energy operation
AU - Chellappa, Srivatsan
AU - Ramamurthy, Chandarasekaran
AU - Vashishtha, Vinay
AU - Clark, Lawrence T.
N1 - Publisher Copyright:
© 2015 IEEE.
PY - 2015/4/13
Y1 - 2015/4/13
N2 - Power dissipation is a major concern in sub-nanometer IC designs with technology scaling pushing towards higher clock frequencies. Techniques such as dynamic voltage (and frequency) scaling (DVS) to minimize power while providing good throughput have become commonplace. This paper presents a fully pipelined 256-bit key advanced encryption system (AES) design implemented with power-saving pulse-clocked latches as pipeline flip-flops that supports pipeline collapse, whereby pipeline stages can be unified by making stage latches transparent. The design is fabricated on a foundry 90-nm low standby power process. Measured results show the design is capable of 64 Gb/s encryption, limited by the I/O speed. A 7.6% decrease in the energy per operation beyond DVS power reduction using pipeline stage unification (PSU) is obtained.
AB - Power dissipation is a major concern in sub-nanometer IC designs with technology scaling pushing towards higher clock frequencies. Techniques such as dynamic voltage (and frequency) scaling (DVS) to minimize power while providing good throughput have become commonplace. This paper presents a fully pipelined 256-bit key advanced encryption system (AES) design implemented with power-saving pulse-clocked latches as pipeline flip-flops that supports pipeline collapse, whereby pipeline stages can be unified by making stage latches transparent. The design is fabricated on a foundry 90-nm low standby power process. Measured results show the design is capable of 64 Gb/s encryption, limited by the I/O speed. A 7.6% decrease in the energy per operation beyond DVS power reduction using pipeline stage unification (PSU) is obtained.
KW - IC power
KW - advanced encryption standard
KW - dynamic voltage scaling
KW - pipeline stage unification
KW - pulse latch
UR - http://www.scopus.com/inward/record.url?scp=84944319119&partnerID=8YFLogxK
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U2 - 10.1109/ISQED.2015.7085425
DO - 10.1109/ISQED.2015.7085425
M3 - Conference contribution
AN - SCOPUS:84944319119
T3 - Proceedings - International Symposium on Quality Electronic Design, ISQED
SP - 201
EP - 206
BT - Proceedings of the 16th International Symposium on Quality Electronic Design, ISQED 2015
PB - IEEE Computer Society
T2 - 16th International Symposium on Quality Electronic Design, ISQED 2015
Y2 - 2 March 2015 through 4 March 2015
ER -