TY - GEN
T1 - Adaptive reduction of the frequency search space for multi-vdd digital circuits
AU - Suresh, Chandra K H
AU - Yilmaz, Ender
AU - Ozev, Sule
AU - Sinanoglu, Ozgur
PY - 2013
Y1 - 2013
N2 - Increasing process variations, coupled with the need for highly adaptable circuits, bring about tough new challenges in terms of circuit testing. Circuit adaptation for process and workload variability require costly characterization/test cycles for each chip, in order to extract particular Vdd/fmax behavior of the die under test. This paper aims at adaptively reducing the search space for fmax at multiple levels by reusing the information previously obtained from the DUT during test-time. The proposed adaptive solution reduces the test/characterization time and costs at no area or test overhead.
AB - Increasing process variations, coupled with the need for highly adaptable circuits, bring about tough new challenges in terms of circuit testing. Circuit adaptation for process and workload variability require costly characterization/test cycles for each chip, in order to extract particular Vdd/fmax behavior of the die under test. This paper aims at adaptively reducing the search space for fmax at multiple levels by reusing the information previously obtained from the DUT during test-time. The proposed adaptive solution reduces the test/characterization time and costs at no area or test overhead.
UR - http://www.scopus.com/inward/record.url?scp=84885576738&partnerID=8YFLogxK
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U2 - 10.7873/date.2013.072
DO - 10.7873/date.2013.072
M3 - Conference contribution
AN - SCOPUS:84885576738
SN - 9783981537000
T3 - Proceedings -Design, Automation and Test in Europe, DATE
SP - 292
EP - 295
BT - Proceedings - Design, Automation and Test in Europe, DATE 2013
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 16th Design, Automation and Test in Europe Conference and Exhibition, DATE 2013
Y2 - 18 March 2013 through 22 March 2013
ER -