Adaptive reduced bit-width Instruction Set Architecture (adapt-rISA)

Sandro Neves Soares, Ashok Halambi, Aviral Shrivastava, Flávio Rech Wagner, Nikil Dutt

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

RISA (reduced bit-width Instruction Set Architecture) is an important architectural feature to reduce code size, which continues to be an extremely important concern for low-end embedded systems. rISA reduces code size by expressing parts of the application in terms of low bit-width instructions. ARM-Thumb, ARCcompact and MIPS16/32 are popular examples. With the intent to exploit the dynamically changing working instruction set of today's complex software, ARM 11 now comes with two rISAs, which can be interleaved in the application binary. However, it was demonstrated that the code compression achieved by rISA is extremely sensitive on the selected rISA design. Therefore, it is important to design the optimal rISA for a given embedded application. The one optimal rISA per application approach has already been explored by previous works. In this paper, we present a scheme to design a multiple rISA architecture for embedded systems. Our experiments on MiBench report an average of 19% code compression and up to 7% power reduction of instruction memory when compared to previous approaches using only one optimal rISA.

Original languageEnglish (US)
Title of host publicationProceedings - 17th IFIP International Conference on Very Large Scale Integration, VLSI-SoC 2009
PublisherIEEE Computer Society
Pages47-52
Number of pages6
ISBN (Print)9781457702365
DOIs
StatePublished - Jan 1 2009
Event17th IFIP International Conference on Very Large Scale Integration, VLSI-SoC 2009 - Florianopolis, Brazil
Duration: Oct 12 2009Oct 14 2009

Publication series

NameProceedings - 17th IFIP International Conference on Very Large Scale Integration, VLSI-SoC 2009

Other

Other17th IFIP International Conference on Very Large Scale Integration, VLSI-SoC 2009
CountryBrazil
CityFlorianopolis
Period10/12/0910/14/09

Keywords

  • Embedded systems design
  • code compression
  • power reduction

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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