Adaptive reduced bit-width Instruction Set Architecture (adapt-rISA)

Sandro Neves Soares; Ashok Halambi; Aviral Shrivastava; Flávio Rech Wagner; Nikil Dutt

doi:10.1109/VLSISOC.2009.6041329

Adaptive reduced bit-width Instruction Set Architecture (adapt-rISA)

Sandro Neves Soares, Ashok Halambi, Aviral Shrivastava, Flávio Rech Wagner, Nikil Dutt

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Scopus citations

Abstract

RISA (reduced bit-width Instruction Set Architecture) is an important architectural feature to reduce code size, which continues to be an extremely important concern for low-end embedded systems. rISA reduces code size by expressing parts of the application in terms of low bit-width instructions. ARM-Thumb, ARCcompact and MIPS16/32 are popular examples. With the intent to exploit the dynamically changing working instruction set of today's complex software, ARM 11 now comes with two rISAs, which can be interleaved in the application binary. However, it was demonstrated that the code compression achieved by rISA is extremely sensitive on the selected rISA design. Therefore, it is important to design the optimal rISA for a given embedded application. The one optimal rISA per application approach has already been explored by previous works. In this paper, we present a scheme to design a multiple rISA architecture for embedded systems. Our experiments on MiBench report an average of 19% code compression and up to 7% power reduction of instruction memory when compared to previous approaches using only one optimal rISA.

Original language	English (US)
Title of host publication	Proceedings - 17th IFIP International Conference on Very Large Scale Integration, VLSI-SoC 2009
Publisher	IEEE Computer Society
Pages	47-52
Number of pages	6
ISBN (Print)	9781457702365
DOIs	https://doi.org/10.1109/VLSISOC.2009.6041329
State	Published - 2009
Event	17th IFIP International Conference on Very Large Scale Integration, VLSI-SoC 2009 - Florianopolis, Brazil Duration: Oct 12 2009 → Oct 14 2009

Publication series

Name	Proceedings - 17th IFIP International Conference on Very Large Scale Integration, VLSI-SoC 2009

Other

Other	17th IFIP International Conference on Very Large Scale Integration, VLSI-SoC 2009
Country/Territory	Brazil
City	Florianopolis
Period	10/12/09 → 10/14/09

Keywords

Embedded systems design
code compression
power reduction

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/VLSISOC.2009.6041329

Cite this

Neves Soares, S., Halambi, A., Shrivastava, A., Wagner, F. R., & Dutt, N. (2009). Adaptive reduced bit-width Instruction Set Architecture (adapt-rISA). In Proceedings - 17th IFIP International Conference on Very Large Scale Integration, VLSI-SoC 2009 (pp. 47-52). Article 6041329 (Proceedings - 17th IFIP International Conference on Very Large Scale Integration, VLSI-SoC 2009). IEEE Computer Society. https://doi.org/10.1109/VLSISOC.2009.6041329

Adaptive reduced bit-width Instruction Set Architecture (adapt-rISA). / Neves Soares, Sandro; Halambi, Ashok; Shrivastava, Aviral et al.
Proceedings - 17th IFIP International Conference on Very Large Scale Integration, VLSI-SoC 2009. IEEE Computer Society, 2009. p. 47-52 6041329 (Proceedings - 17th IFIP International Conference on Very Large Scale Integration, VLSI-SoC 2009).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Neves Soares, S, Halambi, A, Shrivastava, A, Wagner, FR & Dutt, N 2009, Adaptive reduced bit-width Instruction Set Architecture (adapt-rISA). in Proceedings - 17th IFIP International Conference on Very Large Scale Integration, VLSI-SoC 2009., 6041329, Proceedings - 17th IFIP International Conference on Very Large Scale Integration, VLSI-SoC 2009, IEEE Computer Society, pp. 47-52, 17th IFIP International Conference on Very Large Scale Integration, VLSI-SoC 2009, Florianopolis, Brazil, 10/12/09. https://doi.org/10.1109/VLSISOC.2009.6041329

Neves Soares S, Halambi A, Shrivastava A, Wagner FR, Dutt N. Adaptive reduced bit-width Instruction Set Architecture (adapt-rISA). In Proceedings - 17th IFIP International Conference on Very Large Scale Integration, VLSI-SoC 2009. IEEE Computer Society. 2009. p. 47-52. 6041329. (Proceedings - 17th IFIP International Conference on Very Large Scale Integration, VLSI-SoC 2009). doi: 10.1109/VLSISOC.2009.6041329

Neves Soares, Sandro ; Halambi, Ashok ; Shrivastava, Aviral et al. / Adaptive reduced bit-width Instruction Set Architecture (adapt-rISA). Proceedings - 17th IFIP International Conference on Very Large Scale Integration, VLSI-SoC 2009. IEEE Computer Society, 2009. pp. 47-52 (Proceedings - 17th IFIP International Conference on Very Large Scale Integration, VLSI-SoC 2009).

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Adaptive reduced bit-width Instruction Set Architecture (adapt-rISA)

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