Adaptive reduced bit-width Instruction Set Architecture (adapt-rISA)

Sandro Neves Soares, Ashok Halambi, Aviral Shrivastava, Flávio Rech Wagner, Nikil Dutt

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

RISA (reduced bit-width Instruction Set Architecture) is an important architectural feature to reduce code size, which continues to be an extremely important concern for low-end embedded systems. rISA reduces code size by expressing parts of the application in terms of low bit-width instructions. ARM-Thumb, ARCcompact and MIPS16/32 are popular examples. With the intent to exploit the dynamically changing working instruction set of today's complex software, ARM 11 now comes with two rISAs, which can be interleaved in the application binary. However, it was demonstrated that the code compression achieved by rISA is extremely sensitive on the selected rISA design. Therefore, it is important to design the optimal rISA for a given embedded application. The one optimal rISA per application approach has already been explored by previous works. In this paper, we present a scheme to design a multiple rISA architecture for embedded systems. Our experiments on MiBench report an average of 19% code compression and up to 7% power reduction of instruction memory when compared to previous approaches using only one optimal rISA.

Original languageEnglish (US)
Title of host publicationProceedings - 17th IFIP International Conference on Very Large Scale Integration, VLSI-SoC 2009
Pages47-52
Number of pages6
DOIs
StatePublished - 2011
Event17th IFIP International Conference on Very Large Scale Integration, VLSI-SoC 2009 - Florianopolis, Brazil
Duration: Oct 12 2009Oct 14 2009

Other

Other17th IFIP International Conference on Very Large Scale Integration, VLSI-SoC 2009
CountryBrazil
CityFlorianopolis
Period10/12/0910/14/09

Fingerprint

Embedded systems
Data storage equipment
Experiments

Keywords

  • code compression
  • Embedded systems design
  • power reduction

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Neves Soares, S., Halambi, A., Shrivastava, A., Wagner, F. R., & Dutt, N. (2011). Adaptive reduced bit-width Instruction Set Architecture (adapt-rISA). In Proceedings - 17th IFIP International Conference on Very Large Scale Integration, VLSI-SoC 2009 (pp. 47-52). [6041329] https://doi.org/10.1109/VLSISOC.2009.6041329

Adaptive reduced bit-width Instruction Set Architecture (adapt-rISA). / Neves Soares, Sandro; Halambi, Ashok; Shrivastava, Aviral; Wagner, Flávio Rech; Dutt, Nikil.

Proceedings - 17th IFIP International Conference on Very Large Scale Integration, VLSI-SoC 2009. 2011. p. 47-52 6041329.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Neves Soares, S, Halambi, A, Shrivastava, A, Wagner, FR & Dutt, N 2011, Adaptive reduced bit-width Instruction Set Architecture (adapt-rISA). in Proceedings - 17th IFIP International Conference on Very Large Scale Integration, VLSI-SoC 2009., 6041329, pp. 47-52, 17th IFIP International Conference on Very Large Scale Integration, VLSI-SoC 2009, Florianopolis, Brazil, 10/12/09. https://doi.org/10.1109/VLSISOC.2009.6041329
Neves Soares S, Halambi A, Shrivastava A, Wagner FR, Dutt N. Adaptive reduced bit-width Instruction Set Architecture (adapt-rISA). In Proceedings - 17th IFIP International Conference on Very Large Scale Integration, VLSI-SoC 2009. 2011. p. 47-52. 6041329 https://doi.org/10.1109/VLSISOC.2009.6041329
Neves Soares, Sandro ; Halambi, Ashok ; Shrivastava, Aviral ; Wagner, Flávio Rech ; Dutt, Nikil. / Adaptive reduced bit-width Instruction Set Architecture (adapt-rISA). Proceedings - 17th IFIP International Conference on Very Large Scale Integration, VLSI-SoC 2009. 2011. pp. 47-52
@inproceedings{f79525b7f11c4685b14daf323a6dae0e,
title = "Adaptive reduced bit-width Instruction Set Architecture (adapt-rISA)",
abstract = "RISA (reduced bit-width Instruction Set Architecture) is an important architectural feature to reduce code size, which continues to be an extremely important concern for low-end embedded systems. rISA reduces code size by expressing parts of the application in terms of low bit-width instructions. ARM-Thumb, ARCcompact and MIPS16/32 are popular examples. With the intent to exploit the dynamically changing working instruction set of today's complex software, ARM 11 now comes with two rISAs, which can be interleaved in the application binary. However, it was demonstrated that the code compression achieved by rISA is extremely sensitive on the selected rISA design. Therefore, it is important to design the optimal rISA for a given embedded application. The one optimal rISA per application approach has already been explored by previous works. In this paper, we present a scheme to design a multiple rISA architecture for embedded systems. Our experiments on MiBench report an average of 19{\%} code compression and up to 7{\%} power reduction of instruction memory when compared to previous approaches using only one optimal rISA.",
keywords = "code compression, Embedded systems design, power reduction",
author = "{Neves Soares}, Sandro and Ashok Halambi and Aviral Shrivastava and Wagner, {Fl{\'a}vio Rech} and Nikil Dutt",
year = "2011",
doi = "10.1109/VLSISOC.2009.6041329",
language = "English (US)",
isbn = "9781457702365",
pages = "47--52",
booktitle = "Proceedings - 17th IFIP International Conference on Very Large Scale Integration, VLSI-SoC 2009",

}

TY - GEN

T1 - Adaptive reduced bit-width Instruction Set Architecture (adapt-rISA)

AU - Neves Soares, Sandro

AU - Halambi, Ashok

AU - Shrivastava, Aviral

AU - Wagner, Flávio Rech

AU - Dutt, Nikil

PY - 2011

Y1 - 2011

N2 - RISA (reduced bit-width Instruction Set Architecture) is an important architectural feature to reduce code size, which continues to be an extremely important concern for low-end embedded systems. rISA reduces code size by expressing parts of the application in terms of low bit-width instructions. ARM-Thumb, ARCcompact and MIPS16/32 are popular examples. With the intent to exploit the dynamically changing working instruction set of today's complex software, ARM 11 now comes with two rISAs, which can be interleaved in the application binary. However, it was demonstrated that the code compression achieved by rISA is extremely sensitive on the selected rISA design. Therefore, it is important to design the optimal rISA for a given embedded application. The one optimal rISA per application approach has already been explored by previous works. In this paper, we present a scheme to design a multiple rISA architecture for embedded systems. Our experiments on MiBench report an average of 19% code compression and up to 7% power reduction of instruction memory when compared to previous approaches using only one optimal rISA.

AB - RISA (reduced bit-width Instruction Set Architecture) is an important architectural feature to reduce code size, which continues to be an extremely important concern for low-end embedded systems. rISA reduces code size by expressing parts of the application in terms of low bit-width instructions. ARM-Thumb, ARCcompact and MIPS16/32 are popular examples. With the intent to exploit the dynamically changing working instruction set of today's complex software, ARM 11 now comes with two rISAs, which can be interleaved in the application binary. However, it was demonstrated that the code compression achieved by rISA is extremely sensitive on the selected rISA design. Therefore, it is important to design the optimal rISA for a given embedded application. The one optimal rISA per application approach has already been explored by previous works. In this paper, we present a scheme to design a multiple rISA architecture for embedded systems. Our experiments on MiBench report an average of 19% code compression and up to 7% power reduction of instruction memory when compared to previous approaches using only one optimal rISA.

KW - code compression

KW - Embedded systems design

KW - power reduction

UR - http://www.scopus.com/inward/record.url?scp=80555154157&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=80555154157&partnerID=8YFLogxK

U2 - 10.1109/VLSISOC.2009.6041329

DO - 10.1109/VLSISOC.2009.6041329

M3 - Conference contribution

AN - SCOPUS:80555154157

SN - 9781457702365

SP - 47

EP - 52

BT - Proceedings - 17th IFIP International Conference on Very Large Scale Integration, VLSI-SoC 2009

ER -