TY - GEN
T1 - Adaptive manycore architectures for big data computing
AU - Doppa, Janardhan Rao
AU - Kim, Ryan Gary
AU - Isakov, Mihailo
AU - Kinsy, Michel A.
AU - Kwon, Hyoukjun
AU - Krishna, Tushar
N1 - Publisher Copyright:
© 2017 Association for Computing Machinery.
PY - 2017/10/19
Y1 - 2017/10/19
N2 - This work presents a cross-layer design of an adaptive manycore architecture to address the computational needs of emerging big data applications within the technological constraints of power and reliability. From the circuits end, we present links with reconfigurable repeaters that allow single-cycle traversals across multiple hops, creating fast single-cycle paths on demand. At the microarchitecture end, we present a router with bi-directional links, unified virtual channel (VC) structure, and the ability to perform self-monitoring and self-configuration around faults. We present our vision for self-aware manycore architectures and argue that machine learning techniques are very appropriate to efficiently control various configurable on-chip resources in order to realize this vision. We provide concrete learning algorithms for core and NoC reconfiguration; and dynamic power management to improve the performance, energyefficiency, and reliability over static designs to meet the demands of big data computing. We also discuss future challenges to push the state-of-the-art on fully adaptive manycore architectures.
AB - This work presents a cross-layer design of an adaptive manycore architecture to address the computational needs of emerging big data applications within the technological constraints of power and reliability. From the circuits end, we present links with reconfigurable repeaters that allow single-cycle traversals across multiple hops, creating fast single-cycle paths on demand. At the microarchitecture end, we present a router with bi-directional links, unified virtual channel (VC) structure, and the ability to perform self-monitoring and self-configuration around faults. We present our vision for self-aware manycore architectures and argue that machine learning techniques are very appropriate to efficiently control various configurable on-chip resources in order to realize this vision. We provide concrete learning algorithms for core and NoC reconfiguration; and dynamic power management to improve the performance, energyefficiency, and reliability over static designs to meet the demands of big data computing. We also discuss future challenges to push the state-of-the-art on fully adaptive manycore architectures.
KW - Adaptive manycore architectures
KW - Big data computing
KW - Interconnect networks
KW - Machine learning
KW - Power management
UR - http://www.scopus.com/inward/record.url?scp=85035784346&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85035784346&partnerID=8YFLogxK
U2 - 10.1145/3130218.3130236
DO - 10.1145/3130218.3130236
M3 - Conference contribution
AN - SCOPUS:85035784346
T3 - 2017 11th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2017
BT - 2017 11th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2017
PB - Association for Computing Machinery, Inc
T2 - 11th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2017
Y2 - 19 October 2017 through 20 October 2017
ER -