This paper addresses the important problem of defect level estimation. For more than 30 years, there have been published models which are commonly used to estimate the time zero test escape rate of digital logic designs. However, estimating escape rate for analog circuits is much more challenging. This paper applies importance sampling techniques to this problem to arrive at a much more practical method of analog defect level computation.
ASJC Scopus subject areas
- Hardware and Architecture
- Electrical and Electronic Engineering