TY - JOUR
T1 - Adaptive blocker rejection continuous-time ∑Δ ADC for mobile wiMAX applications
AU - Kim, Hyungseok
AU - Lee, Junghan
AU - Copani, Tino
AU - Bazarjani, Seyfi
AU - Kiaei, Sayfe
AU - Bakkaloglu, Bertan
N1 - Funding Information:
Manuscript received January 31, 2009; revised May 07, 2009. Current version published September 28, 2009. This paper was approved by Associate Editor David Nairn. This work was supported by Qualcomm Inc. and Connection One NSF I/UCRC. H. Kim, J. Lee, T. Copani, S. Kiaei, and B. Bakkaloglu are with Arizona State University, Tempe, AZ 85287 USA (e-mail: hyungseok@asu.edu). S. Bazarjani is with Qualcomm Inc., San Diego, CA 92121 USA. Digital Object Identifier 10.1109/JSSC.2009.2028053
PY - 2009/10
Y1 - 2009/10
N2 - An adaptive blocker-rejection wideband continuous-time (CT) sigma-delta (∑Δ) analog-to-digital converter (ADC) is presented. An integrated blocker detector reconfigures the ADC loop architecture to avoid overloading in the presence of strong interferers, improving receiver channel selectivity and sensitivity without increasing its dynamic range (DR) requirements. The adaptive operation relaxes receiver baseband channel filtering requirements for a Worldwide Inter-operability for Microwave Access (WiMAX, IEEE 802.16e) receiver. The ADC achieves 71 dB of dynamic range (DR), 65 dB of peak SNDR and 68 dB of peak SNR over a 10 MHz signal bandwidth, consuming 18 mW from a 1.2 V supply. The ADC system reconfigures the loop filter topology within 51 μs, improving receiver selectivity without any transient impact on BER. In the blocker suppression mode, the ADC can withstand 30 dBc blocker at the adjacent channel, achieving -22 dB error vector magnitude (EVM) with a 24 Mb/s 16-QAM signal. The IC is fabricated on a 130 nm 8-level metal, metalinsulatormetal (MIM) capacitor, CMOS technology, occupying 1.5×0.9 mm2 silicon area.
AB - An adaptive blocker-rejection wideband continuous-time (CT) sigma-delta (∑Δ) analog-to-digital converter (ADC) is presented. An integrated blocker detector reconfigures the ADC loop architecture to avoid overloading in the presence of strong interferers, improving receiver channel selectivity and sensitivity without increasing its dynamic range (DR) requirements. The adaptive operation relaxes receiver baseband channel filtering requirements for a Worldwide Inter-operability for Microwave Access (WiMAX, IEEE 802.16e) receiver. The ADC achieves 71 dB of dynamic range (DR), 65 dB of peak SNDR and 68 dB of peak SNR over a 10 MHz signal bandwidth, consuming 18 mW from a 1.2 V supply. The ADC system reconfigures the loop filter topology within 51 μs, improving receiver selectivity without any transient impact on BER. In the blocker suppression mode, the ADC can withstand 30 dBc blocker at the adjacent channel, achieving -22 dB error vector magnitude (EVM) with a 24 Mb/s 16-QAM signal. The IC is fabricated on a 130 nm 8-level metal, metalinsulatormetal (MIM) capacitor, CMOS technology, occupying 1.5×0.9 mm2 silicon area.
KW - Adaptive blocker rejection
KW - Analog-to-digital conversion
KW - Continuous-time ∑Δ ADC
KW - WiMAX
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U2 - 10.1109/JSSC.2009.2028053
DO - 10.1109/JSSC.2009.2028053
M3 - Article
AN - SCOPUS:70350614441
SN - 0018-9200
VL - 44
SP - 2766
EP - 2779
JO - IEEE Journal of Solid-State Circuits
JF - IEEE Journal of Solid-State Circuits
IS - 10
M1 - 19
ER -