An adaptive blocker-rejection wideband continuous-time (CT) sigma-delta (∑Δ) analog-to-digital converter (ADC) is presented. An integrated blocker detector reconfigures the ADC loop architecture to avoid overloading in the presence of strong interferers, improving receiver channel selectivity and sensitivity without increasing its dynamic range (DR) requirements. The adaptive operation relaxes receiver baseband channel filtering requirements for a Worldwide Inter-operability for Microwave Access (WiMAX, IEEE 802.16e) receiver. The ADC achieves 71 dB of dynamic range (DR), 65 dB of peak SNDR and 68 dB of peak SNR over a 10 MHz signal bandwidth, consuming 18 mW from a 1.2 V supply. The ADC system reconfigures the loop filter topology within 51 μs, improving receiver selectivity without any transient impact on BER. In the blocker suppression mode, the ADC can withstand 30 dBc blocker at the adjacent channel, achieving -22 dB error vector magnitude (EVM) with a 24 Mb/s 16-QAM signal. The IC is fabricated on a 130 nm 8-level metal, metalinsulatormetal (MIM) capacitor, CMOS technology, occupying 1.5×0.9 mm2 silicon area.
- Adaptive blocker rejection
- Analog-to-digital conversion
- Continuous-time ∑Δ ADC
ASJC Scopus subject areas
- Electrical and Electronic Engineering