Achieving the shortest clock period by inserting the minimum amount of delay

Shangzhi Sun, David H.C. Du, Guoliang Xue

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

The performance of a circuit depends on its clock period. The shorter a valid clock period is, the better the performance is. The clock period is tightly related to the difference between the longest propagation delay and the shortest propagation delay from primary inputs to primaxy outputs. The objective of this paper is to minimize the amount of delay inserted while achieving the shortest clock period. Inserting delay buffers is done after traditional delay optimization. We propose an optimal algorithm based on a novel linear programming formulation. Our algorithm can also be used to solve similar delay buffer problems.

Original languageEnglish (US)
Title of host publicationAlgorithms and Computation - 5th International Symposium, ISAAC 1994, Proceedings
EditorsDing-Zhu Du, Ding-Zhu Du, Xiang-Sun Zhang
PublisherSpringer Verlag
Pages669-677
Number of pages9
ISBN (Print)9783540583257
DOIs
StatePublished - 1994
Externally publishedYes
Event5th Annual International Symposium on Algorithms and Computation, ISAAC 1994 - Beijing, China
Duration: Aug 25 1994Aug 27 1994

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume834 LNCS
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349

Other

Other5th Annual International Symposium on Algorithms and Computation, ISAAC 1994
Country/TerritoryChina
CityBeijing
Period8/25/948/27/94

ASJC Scopus subject areas

  • Theoretical Computer Science
  • General Computer Science

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